a4193c8a4b
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@874 c046a42c-6fe2-441c-8c8c-71466251a162
446 lines
12 KiB
C
446 lines
12 KiB
C
/*
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* QEMU generic PPC hardware System Emulator
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*
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* Copyright (c) 2003-2004 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h"
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/*****************************************************************************/
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/* PPC time base and decrementer emulation */
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//#define DEBUG_TB
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struct ppc_tb_t {
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/* Time base management */
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int64_t tb_offset; /* Compensation */
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uint32_t tb_freq; /* TB frequency */
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/* Decrementer management */
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uint64_t decr_next; /* Tick for next decr interrupt */
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struct QEMUTimer *decr_timer;
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};
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static inline uint64_t cpu_ppc_get_tb (ppc_tb_t *tb_env)
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{
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/* TB time in tb periods */
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return muldiv64(qemu_get_clock(vm_clock) + tb_env->tb_offset,
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tb_env->tb_freq, ticks_per_sec);
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}
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uint32_t cpu_ppc_load_tbl (CPUState *env)
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{
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ppc_tb_t *tb_env = env->tb_env;
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uint64_t tb;
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tb = cpu_ppc_get_tb(tb_env);
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#ifdef DEBUG_TB
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{
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static int last_time;
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int now;
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now = time(NULL);
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if (last_time != now) {
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last_time = now;
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printf("%s: tb=0x%016lx %d %08lx\n",
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__func__, tb, now, tb_env->tb_offset);
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}
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}
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#endif
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return tb & 0xFFFFFFFF;
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}
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uint32_t cpu_ppc_load_tbu (CPUState *env)
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{
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ppc_tb_t *tb_env = env->tb_env;
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uint64_t tb;
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tb = cpu_ppc_get_tb(tb_env);
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#ifdef DEBUG_TB
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printf("%s: tb=0x%016lx\n", __func__, tb);
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#endif
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return tb >> 32;
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}
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static void cpu_ppc_store_tb (ppc_tb_t *tb_env, uint64_t value)
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{
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tb_env->tb_offset = muldiv64(value, ticks_per_sec, tb_env->tb_freq)
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- qemu_get_clock(vm_clock);
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#ifdef DEBUG_TB
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printf("%s: tb=0x%016lx offset=%08x\n", __func__, value);
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#endif
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}
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void cpu_ppc_store_tbu (CPUState *env, uint32_t value)
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{
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ppc_tb_t *tb_env = env->tb_env;
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cpu_ppc_store_tb(tb_env,
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((uint64_t)value << 32) | cpu_ppc_load_tbl(env));
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}
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void cpu_ppc_store_tbl (CPUState *env, uint32_t value)
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{
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ppc_tb_t *tb_env = env->tb_env;
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cpu_ppc_store_tb(tb_env,
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((uint64_t)cpu_ppc_load_tbu(env) << 32) | value);
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}
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uint32_t cpu_ppc_load_decr (CPUState *env)
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{
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ppc_tb_t *tb_env = env->tb_env;
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uint32_t decr;
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decr = muldiv64(tb_env->decr_next - qemu_get_clock(vm_clock),
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tb_env->tb_freq, ticks_per_sec);
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#ifdef DEBUG_TB
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printf("%s: 0x%08x\n", __func__, decr);
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#endif
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return decr;
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}
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/* When decrementer expires,
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* all we need to do is generate or queue a CPU exception
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*/
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static inline void cpu_ppc_decr_excp (CPUState *env)
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{
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/* Raise it */
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#ifdef DEBUG_TB
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printf("raise decrementer exception\n");
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#endif
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cpu_interrupt(env, CPU_INTERRUPT_TIMER);
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}
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static void _cpu_ppc_store_decr (CPUState *env, uint32_t decr,
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uint32_t value, int is_excp)
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{
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ppc_tb_t *tb_env = env->tb_env;
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uint64_t now, next;
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#ifdef DEBUG_TB
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printf("%s: 0x%08x => 0x%08x\n", __func__, decr, value);
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#endif
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now = qemu_get_clock(vm_clock);
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next = now + muldiv64(value, ticks_per_sec, tb_env->tb_freq);
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if (is_excp)
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next += tb_env->decr_next - now;
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if (next == now)
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next++;
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tb_env->decr_next = next;
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/* Adjust timer */
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qemu_mod_timer(tb_env->decr_timer, next);
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/* If we set a negative value and the decrementer was positive,
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* raise an exception.
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*/
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if ((value & 0x80000000) && !(decr & 0x80000000))
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cpu_ppc_decr_excp(env);
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}
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void cpu_ppc_store_decr (CPUState *env, uint32_t value)
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{
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_cpu_ppc_store_decr(env, cpu_ppc_load_decr(env), value, 0);
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}
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static void cpu_ppc_decr_cb (void *opaque)
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{
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_cpu_ppc_store_decr(opaque, 0x00000000, 0xFFFFFFFF, 1);
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}
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/* Set up (once) timebase frequency (in Hz) */
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ppc_tb_t *cpu_ppc_tb_init (CPUState *env, uint32_t freq)
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{
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ppc_tb_t *tb_env;
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tb_env = qemu_mallocz(sizeof(ppc_tb_t));
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if (tb_env == NULL)
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return NULL;
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env->tb_env = tb_env;
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if (tb_env->tb_freq == 0 || 1) {
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tb_env->tb_freq = freq;
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/* Create new timer */
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tb_env->decr_timer =
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qemu_new_timer(vm_clock, &cpu_ppc_decr_cb, env);
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/* There is a bug in 2.4 kernels:
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* if a decrementer exception is pending when it enables msr_ee,
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* it's not ready to handle it...
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*/
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_cpu_ppc_store_decr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0);
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}
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return tb_env;
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}
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#if 0
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/*****************************************************************************/
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/* Handle system reset (for now, just stop emulation) */
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void cpu_ppc_reset (CPUState *env)
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{
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printf("Reset asked... Stop emulation\n");
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abort();
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}
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#endif
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static void PPC_io_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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cpu_outb(NULL, addr & 0xffff, value);
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}
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static uint32_t PPC_io_readb (void *opaque, target_phys_addr_t addr)
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{
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uint32_t ret = cpu_inb(NULL, addr & 0xffff);
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return ret;
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}
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static void PPC_io_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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#ifdef TARGET_WORDS_BIGENDIAN
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value = bswap16(value);
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#endif
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cpu_outw(NULL, addr & 0xffff, value);
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}
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static uint32_t PPC_io_readw (void *opaque, target_phys_addr_t addr)
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{
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uint32_t ret = cpu_inw(NULL, addr & 0xffff);
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#ifdef TARGET_WORDS_BIGENDIAN
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ret = bswap16(ret);
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#endif
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return ret;
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}
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static void PPC_io_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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#ifdef TARGET_WORDS_BIGENDIAN
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value = bswap32(value);
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#endif
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cpu_outl(NULL, addr & 0xffff, value);
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}
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static uint32_t PPC_io_readl (void *opaque, target_phys_addr_t addr)
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{
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uint32_t ret = cpu_inl(NULL, addr & 0xffff);
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#ifdef TARGET_WORDS_BIGENDIAN
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ret = bswap32(ret);
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#endif
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return ret;
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}
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CPUWriteMemoryFunc *PPC_io_write[] = {
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&PPC_io_writeb,
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&PPC_io_writew,
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&PPC_io_writel,
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};
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CPUReadMemoryFunc *PPC_io_read[] = {
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&PPC_io_readb,
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&PPC_io_readw,
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&PPC_io_readl,
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};
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/*****************************************************************************/
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/* Debug port */
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void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val)
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{
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addr &= 0xF;
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switch (addr) {
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case 0:
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printf("%c", val);
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break;
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case 1:
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printf("\n");
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fflush(stdout);
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break;
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case 2:
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printf("Set loglevel to %04x\n", val);
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cpu_set_log(val);
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break;
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}
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}
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/*****************************************************************************/
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/* NVRAM helpers */
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void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value)
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{
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m48t59_set_addr(nvram, addr);
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m48t59_write(nvram, value);
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}
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uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr)
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{
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m48t59_set_addr(nvram, addr);
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return m48t59_read(nvram);
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}
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void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
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{
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m48t59_set_addr(nvram, addr);
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m48t59_write(nvram, value >> 8);
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m48t59_set_addr(nvram, addr + 1);
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m48t59_write(nvram, value & 0xFF);
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}
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uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr)
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{
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uint16_t tmp;
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m48t59_set_addr(nvram, addr);
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tmp = m48t59_read(nvram) << 8;
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m48t59_set_addr(nvram, addr + 1);
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tmp |= m48t59_read(nvram);
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return tmp;
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}
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void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
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{
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m48t59_set_addr(nvram, addr);
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m48t59_write(nvram, value >> 24);
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m48t59_set_addr(nvram, addr + 1);
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m48t59_write(nvram, (value >> 16) & 0xFF);
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m48t59_set_addr(nvram, addr + 2);
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m48t59_write(nvram, (value >> 8) & 0xFF);
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m48t59_set_addr(nvram, addr + 3);
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m48t59_write(nvram, value & 0xFF);
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}
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uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr)
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{
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uint32_t tmp;
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m48t59_set_addr(nvram, addr);
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tmp = m48t59_read(nvram) << 24;
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m48t59_set_addr(nvram, addr + 1);
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tmp |= m48t59_read(nvram) << 16;
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m48t59_set_addr(nvram, addr + 2);
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tmp |= m48t59_read(nvram) << 8;
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m48t59_set_addr(nvram, addr + 3);
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tmp |= m48t59_read(nvram);
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return tmp;
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}
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void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
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const unsigned char *str, uint32_t max)
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{
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int i;
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for (i = 0; i < max && str[i] != '\0'; i++) {
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m48t59_set_addr(nvram, addr + i);
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m48t59_write(nvram, str[i]);
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}
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m48t59_set_addr(nvram, addr + max - 1);
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m48t59_write(nvram, '\0');
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}
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int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max)
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{
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int i;
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memset(dst, 0, max);
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for (i = 0; i < max; i++) {
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dst[i] = NVRAM_get_byte(nvram, addr + i);
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if (dst[i] == '\0')
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break;
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}
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return i;
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}
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static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
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{
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uint16_t tmp;
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uint16_t pd, pd1, pd2;
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tmp = prev >> 8;
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pd = prev ^ value;
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pd1 = pd & 0x000F;
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pd2 = ((pd >> 4) & 0x000F) ^ pd1;
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tmp ^= (pd1 << 3) | (pd1 << 8);
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tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
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return tmp;
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}
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uint16_t NVRAM_compute_crc (m48t59_t *nvram, uint32_t start, uint32_t count)
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{
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uint32_t i;
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uint16_t crc = 0xFFFF;
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int odd;
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odd = count & 1;
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count &= ~1;
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for (i = 0; i != count; i++) {
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crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
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}
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if (odd) {
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crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
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}
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return crc;
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}
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int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
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const unsigned char *arch,
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uint32_t RAM_size, int boot_device,
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uint32_t kernel_image, uint32_t kernel_size,
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uint32_t cmdline, uint32_t cmdline_size,
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uint32_t initrd_image, uint32_t initrd_size,
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uint32_t NVRAM_image)
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{
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uint16_t crc;
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/* Set parameters for Open Hack'Ware BIOS */
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NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
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NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */
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NVRAM_set_word(nvram, 0x14, NVRAM_size);
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NVRAM_set_string(nvram, 0x20, arch, 16);
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NVRAM_set_lword(nvram, 0x30, RAM_size);
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NVRAM_set_byte(nvram, 0x34, boot_device);
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NVRAM_set_lword(nvram, 0x38, kernel_image);
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NVRAM_set_lword(nvram, 0x3C, kernel_size);
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NVRAM_set_lword(nvram, 0x40, cmdline);
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NVRAM_set_lword(nvram, 0x44, cmdline_size);
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NVRAM_set_lword(nvram, 0x48, initrd_image);
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NVRAM_set_lword(nvram, 0x4C, initrd_size);
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NVRAM_set_lword(nvram, 0x50, NVRAM_image);
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crc = NVRAM_compute_crc(nvram, 0x00, 0x5C);
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NVRAM_set_word(nvram, 0x5C, crc);
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return 0;
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}
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/*****************************************************************************/
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void ppc_init (int ram_size, int vga_ram_size, int boot_device,
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DisplayState *ds, const char **fd_filename, int snapshot,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename)
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{
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if (prep_enabled) {
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ppc_prep_init(ram_size, vga_ram_size, boot_device, ds, fd_filename,
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snapshot, kernel_filename, kernel_cmdline,
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initrd_filename);
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} else {
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ppc_chrp_init(ram_size, vga_ram_size, boot_device, ds, fd_filename,
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snapshot, kernel_filename, kernel_cmdline,
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initrd_filename);
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}
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}
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