a31768c019
Extend comparison results from mask registers to SEW-width elements, following recommendations in The RISC-V SPEC Volume I (Version 20240411). This aligns with TCG's cmp_vec behavior by expanding compare results to full element width: all 1s for true, all 0s for false. Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com> Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20241007025700.47259-7-zhiwei_liu@linux.alibaba.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
31 lines
688 B
C
31 lines
688 B
C
/* SPDX-License-Identifier: MIT */
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/*
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* Define RISC-V target-specific constraint sets.
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* Copyright (c) 2021 Linaro
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*/
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/*
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* C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
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* Each operand should be a sequence of constraint letters as defined by
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* tcg-target-con-str.h; the constraint combination is inclusive or.
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*/
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C_O0_I1(r)
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C_O0_I2(rZ, r)
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C_O0_I2(rZ, rZ)
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C_O1_I1(r, r)
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C_O1_I2(r, r, ri)
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C_O1_I2(r, r, rI)
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C_O1_I2(r, r, rJ)
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C_O1_I2(r, rZ, rN)
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C_O1_I2(r, rZ, rZ)
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C_N1_I2(r, r, rM)
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C_O1_I4(r, r, rI, rM, rM)
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C_O2_I4(r, r, rZ, rZ, rM, rM)
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C_O0_I2(v, r)
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C_O1_I1(v, r)
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C_O1_I1(v, v)
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C_O1_I2(v, v, v)
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C_O1_I2(v, v, vK)
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C_O1_I2(v, v, vL)
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C_O1_I4(v, v, vL, vK, vK)
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