qemu/target
Paolo Bonzini a290e43f58 target/i386: pcrel: store low bits of physical address in data[0]
For PC-relative translation blocks, env->eip changes during the
execution of a translation block, Therefore, QEMU must be able to
recover an instruction's PC just from the TranslationBlock struct and
the instruction data with.  Because a TB will not span two pages, QEMU
stores all the low bits of EIP in the instruction data and replaces them
in x86_restore_state_to_opc.  Bits 12 and higher (which may vary between
executions of a PCREL TB, since these only use the physical address in
the hash key) are kept unmodified from env->eip.  The assumption is that
these bits of EIP, unlike bits 0-11, will not change as the translation
block executes.

Unfortunately, this is incorrect when the CS base is not aligned to a page.
Then the linear address of the instructions (i.e. the one with the
CS base addred) indeed will never span two pages, but bits 12+ of EIP
can actually change.  For example, if CS base is 0x80262200 and EIP =
0x6FF4, the first instruction in the translation block will be at linear
address 0x802691F4.  Even a very small TB will cross to EIP = 0x7xxx,
while the linear addresses will remain comfortably within a single page.

The fix is simply to use the low bits of the linear address for data[0],
since those don't change.  Then x86_restore_state_to_opc uses tb->cs_base
to compute a temporary linear address (referring to some unknown
instruction in the TB, but with the correct values of bits 12 and higher);
the low bits are replaced with data[0], and EIP is obtained by subtracting
again the CS base.

Huge thanks to Mark Cave-Ayland for the image and initial debugging,
and to Gitlab user @kjliew for help with bisecting another occurrence
of (hopefully!) the same bug.

It should be relatively easy to write a testcase that performs MMIO on
an EIP with different bits 12+ than the first instruction of the translation
block; any help is welcome.

Fixes: e3a79e0e87 ("target/i386: Enable TARGET_TB_PCREL", 2022-10-11)
Cc: qemu-stable@nongnu.org
Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Cc: Richard Henderson <richard.henderson@linaro.org>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1759
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1964
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2012
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
(cherry picked from commit 729ba8e933)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
(Mjt: fixup in target/i386/tcg/tcg-cpu.c target/i386/tcg/translate.c for
 v7.2.0-1839-g2e3afe8e19 "target/i386: Replace `TARGET_TB_PCREL` with `CF_PCREL`")
2024-01-20 17:41:47 +03:00
..
alpha accel/tcg: Remove will_exit argument from cpu_restore_state 2022-11-01 08:31:41 +11:00
arm target/arm/helper: Propagate MDCR_EL2.HPMN into PMCR_EL0.N 2023-12-20 19:11:11 +03:00
avr target/avr: Convert to tcg_ops restore_state_to_opc 2022-10-26 11:11:28 +10:00
cris accel/tcg: Remove will_exit argument from cpu_restore_state 2022-11-01 08:31:41 +11:00
hexagon target/hexagon: Convert to tcg_ops restore_state_to_opc 2022-10-26 11:11:28 +10:00
hppa target/hppa: Move iaoq registers and thus reduce generated code size 2023-08-04 07:33:49 +03:00
i386 target/i386: pcrel: store low bits of physical address in data[0] 2024-01-20 17:41:47 +03:00
loongarch target/loongarch: Fix the CSRRD CPUID instruction on big endian hosts 2023-07-31 09:12:06 +03:00
m68k target/m68k: Fix semihost lseek offset computation 2023-08-03 08:26:26 +03:00
microblaze accel/tcg: Remove will_exit argument from cpu_restore_state 2022-11-01 08:31:41 +11:00
mips target/mips: Fix TX79 LQ/SQ opcodes 2023-11-19 21:15:23 +03:00
nios2 target/nios2: Fix semihost lseek offset computation 2023-08-03 08:26:26 +03:00
openrisc accel/tcg: Remove will_exit argument from cpu_restore_state 2022-11-01 08:31:41 +11:00
ppc target/ppc: Flush inputs to zero with NJ in ppc_store_vscr 2023-09-11 10:53:50 +03:00
riscv target/riscv: Fix mcycle/minstret increment behavior 2024-01-08 19:24:44 +03:00
rx Revert incorrect cflags initialization. 2022-10-26 10:53:41 -04:00
s390x target/s390x: Fix LAE setting a wrong access register 2024-01-13 11:28:02 +03:00
sh4 target/sh4: Mask restore of env->flags from tb->flags 2023-03-29 10:20:04 +03:00
sparc target/sparc: Convert to tcg_ops restore_state_to_opc 2022-10-26 11:11:28 +10:00
tricore target/tricore: Rename tricore_feature 2023-11-19 21:15:23 +03:00
xtensa accel/tcg: Remove will_exit argument from cpu_restore_state 2022-11-01 08:31:41 +11:00
Kconfig hw/loongarch: Add support loongson3 virt machine type. 2022-06-06 18:09:03 +00:00
meson.build target/loongarch: Add target build suport 2022-06-06 18:09:03 +00:00