Bastian Koppelmann a21993c7f9 target/tricore: Fix OPC2_32_RRPW_EXTR for width=0
if width was 0 we would run into the assertion:

qemu-system-tricore: tcg/tcg-op.c:217: tcg_gen_sari_i32: Assertion `arg2 >= 0 && arg2 < 32' failed.o

The instruction manual specifies undefined behaviour for this case. So
we bring this in line with the golden Infineon simlator 'tsim', which
simply writes 0 to the result in case of width=0.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2021-03-14 14:49:01 +01:00
..
2021-03-11 18:55:27 +00:00
2021-03-12 18:56:56 +00:00
2021-03-11 18:55:27 +00:00
2021-03-12 11:30:55 +00:00
2021-03-11 18:55:27 +00:00
2021-03-06 16:18:42 +01:00
2021-03-09 11:26:32 +01:00