Efimov Vasily f999c0de05 ICH9 LPC: handle GSI as qdev GPIO ... The ICH9 LPC bridge has 24 output IRQs connected to GSI. Currently the IRQs are referenced by pointers. The pointers are initialized at startup by direct access to the structure fields. This violates Qemu device model. The patch makes the IRQs handling to use GPIO model. Signed-off-by: Efimov Vasily <real@ispras.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>		2016-06-29 14:03:46 +02:00
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apic_internal.h	cpu/apic: drop icc bus/bridge	2015-10-02 16:22:02 -03:00
apic-msidef.h
apic.h	apic: move target-dependent definitions to cpu.h	2016-05-19 16:42:28 +02:00
ich9.h	ICH9 LPC: handle GSI as qdev GPIO	2016-06-29 14:03:46 +02:00
intel_iommu.h	intel_iommu: large page support	2016-02-06 20:44:10 +02:00
ioapic_internal.h	ioapic: keep RO bits for IOAPIC entry	2016-05-23 16:53:43 +02:00
ioapic.h	pc: move IO_APIC_DEFAULT_ADDRESS to include/hw/i386/ioapic.h	2013-07-29 19:33:32 -05:00
pc.h	port92: handle A20 IRQ as GPIO	2016-06-29 14:03:46 +02:00
topology.h	include: Clean up includes	2016-02-23 12:43:05 +00:00