a0e372f0c4
CPUState::gdb_num_regs replaces num_g_regs. CPUClass::gdb_num_core_regs replaces NUM_CORE_REGS. Allows building gdb_register_coprocessor() for xtensa, too. As a side effect this should fix coprocessor register numbering for SMP. Acked-by: Michael Walle <michael@walle.cc> (for lm32) Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa) Signed-off-by: Andreas Färber <afaerber@suse.de>
519 lines
15 KiB
C
519 lines
15 KiB
C
/*
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* QEMU CPU model
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*
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see
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* <http://www.gnu.org/licenses/gpl-2.0.html>
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*/
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#ifndef QEMU_CPU_H
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#define QEMU_CPU_H
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#include <signal.h>
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#include "hw/qdev-core.h"
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#include "exec/hwaddr.h"
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#include "qemu/thread.h"
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#include "qemu/tls.h"
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#include "qemu/typedefs.h"
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typedef int (*WriteCoreDumpFunction)(void *buf, size_t size, void *opaque);
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/**
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* vaddr:
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* Type wide enough to contain any #target_ulong virtual address.
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*/
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typedef uint64_t vaddr;
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#define VADDR_PRId PRId64
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#define VADDR_PRIu PRIu64
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#define VADDR_PRIo PRIo64
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#define VADDR_PRIx PRIx64
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#define VADDR_PRIX PRIX64
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#define VADDR_MAX UINT64_MAX
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/**
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* SECTION:cpu
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* @section_id: QEMU-cpu
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* @title: CPU Class
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* @short_description: Base class for all CPUs
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*/
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#define TYPE_CPU "cpu"
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#define CPU(obj) OBJECT_CHECK(CPUState, (obj), TYPE_CPU)
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#define CPU_CLASS(class) OBJECT_CLASS_CHECK(CPUClass, (class), TYPE_CPU)
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#define CPU_GET_CLASS(obj) OBJECT_GET_CLASS(CPUClass, (obj), TYPE_CPU)
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typedef struct CPUState CPUState;
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typedef void (*CPUUnassignedAccess)(CPUState *cpu, hwaddr addr,
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bool is_write, bool is_exec, int opaque,
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unsigned size);
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struct TranslationBlock;
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/**
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* CPUClass:
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* @class_by_name: Callback to map -cpu command line model name to an
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* instantiatable CPU type.
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* @reset: Callback to reset the #CPUState to its initial state.
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* @reset_dump_flags: #CPUDumpFlags to use for reset logging.
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* @do_interrupt: Callback for interrupt handling.
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* @do_unassigned_access: Callback for unassigned access handling.
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* @memory_rw_debug: Callback for GDB memory access.
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* @dump_state: Callback for dumping state.
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* @dump_statistics: Callback for dumping statistics.
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* @get_arch_id: Callback for getting architecture-dependent CPU ID.
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* @get_paging_enabled: Callback for inquiring whether paging is enabled.
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* @get_memory_mapping: Callback for obtaining the memory mappings.
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* @set_pc: Callback for setting the Program Counter register.
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* @synchronize_from_tb: Callback for synchronizing state from a TCG
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* #TranslationBlock.
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* @get_phys_page_debug: Callback for obtaining a physical address.
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* @vmsd: State description for migration.
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* @gdb_num_core_regs: Number of core registers accessible to GDB.
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*
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* Represents a CPU family or model.
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*/
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typedef struct CPUClass {
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/*< private >*/
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DeviceClass parent_class;
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/*< public >*/
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ObjectClass *(*class_by_name)(const char *cpu_model);
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void (*reset)(CPUState *cpu);
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int reset_dump_flags;
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void (*do_interrupt)(CPUState *cpu);
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CPUUnassignedAccess do_unassigned_access;
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int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
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uint8_t *buf, int len, bool is_write);
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void (*dump_state)(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
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int flags);
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void (*dump_statistics)(CPUState *cpu, FILE *f,
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fprintf_function cpu_fprintf, int flags);
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int64_t (*get_arch_id)(CPUState *cpu);
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bool (*get_paging_enabled)(const CPUState *cpu);
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void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
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Error **errp);
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void (*set_pc)(CPUState *cpu, vaddr value);
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void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb);
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hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
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int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
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int cpuid, void *opaque);
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int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
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void *opaque);
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int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu,
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int cpuid, void *opaque);
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int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
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void *opaque);
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const struct VMStateDescription *vmsd;
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int gdb_num_core_regs;
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} CPUClass;
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struct KVMState;
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struct kvm_run;
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/**
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* CPUState:
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* @cpu_index: CPU index (informative).
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* @nr_cores: Number of cores within this CPU package.
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* @nr_threads: Number of threads within this CPU.
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* @numa_node: NUMA node this CPU is belonging to.
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* @host_tid: Host thread ID.
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* @running: #true if CPU is currently running (usermode).
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* @created: Indicates whether the CPU thread has been successfully created.
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* @interrupt_request: Indicates a pending interrupt request.
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* @halted: Nonzero if the CPU is in suspended state.
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* @stop: Indicates a pending stop request.
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* @stopped: Indicates the CPU has been artificially stopped.
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* @tcg_exit_req: Set to force TCG to stop executing linked TBs for this
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* CPU and return to its top level loop.
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* @singlestep_enabled: Flags for single-stepping.
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* @env_ptr: Pointer to subclass-specific CPUArchState field.
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* @current_tb: Currently executing TB.
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* @gdb_regs: Additional GDB registers.
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* @gdb_num_regs: Number of total registers accessible to GDB.
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* @next_cpu: Next CPU sharing TB cache.
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* @kvm_fd: vCPU file descriptor for KVM.
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*
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* State of one CPU core or thread.
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*/
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struct CPUState {
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/*< private >*/
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DeviceState parent_obj;
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/*< public >*/
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int nr_cores;
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int nr_threads;
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int numa_node;
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struct QemuThread *thread;
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#ifdef _WIN32
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HANDLE hThread;
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#endif
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int thread_id;
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uint32_t host_tid;
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bool running;
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struct QemuCond *halt_cond;
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struct qemu_work_item *queued_work_first, *queued_work_last;
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bool thread_kicked;
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bool created;
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bool stop;
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bool stopped;
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volatile sig_atomic_t exit_request;
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volatile sig_atomic_t tcg_exit_req;
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uint32_t interrupt_request;
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int singlestep_enabled;
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void *env_ptr; /* CPUArchState */
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struct TranslationBlock *current_tb;
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struct GDBRegisterState *gdb_regs;
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int gdb_num_regs;
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CPUState *next_cpu;
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int kvm_fd;
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bool kvm_vcpu_dirty;
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struct KVMState *kvm_state;
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struct kvm_run *kvm_run;
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/* TODO Move common fields from CPUArchState here. */
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int cpu_index; /* used by alpha TCG */
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uint32_t halted; /* used by alpha, cris, ppc TCG */
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};
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extern CPUState *first_cpu;
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DECLARE_TLS(CPUState *, current_cpu);
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#define current_cpu tls_var(current_cpu)
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/**
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* cpu_paging_enabled:
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* @cpu: The CPU whose state is to be inspected.
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*
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* Returns: %true if paging is enabled, %false otherwise.
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*/
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bool cpu_paging_enabled(const CPUState *cpu);
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/**
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* cpu_get_memory_mapping:
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* @cpu: The CPU whose memory mappings are to be obtained.
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* @list: Where to write the memory mappings to.
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* @errp: Pointer for reporting an #Error.
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*/
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void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
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Error **errp);
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/**
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* cpu_write_elf64_note:
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* @f: pointer to a function that writes memory to a file
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* @cpu: The CPU whose memory is to be dumped
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* @cpuid: ID number of the CPU
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* @opaque: pointer to the CPUState struct
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*/
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int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
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int cpuid, void *opaque);
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/**
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* cpu_write_elf64_qemunote:
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* @f: pointer to a function that writes memory to a file
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* @cpu: The CPU whose memory is to be dumped
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* @cpuid: ID number of the CPU
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* @opaque: pointer to the CPUState struct
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*/
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int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
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void *opaque);
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/**
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* cpu_write_elf32_note:
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* @f: pointer to a function that writes memory to a file
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* @cpu: The CPU whose memory is to be dumped
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* @cpuid: ID number of the CPU
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* @opaque: pointer to the CPUState struct
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*/
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int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
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int cpuid, void *opaque);
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/**
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* cpu_write_elf32_qemunote:
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* @f: pointer to a function that writes memory to a file
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* @cpu: The CPU whose memory is to be dumped
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* @cpuid: ID number of the CPU
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* @opaque: pointer to the CPUState struct
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*/
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int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
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void *opaque);
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/**
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* CPUDumpFlags:
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* @CPU_DUMP_CODE:
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* @CPU_DUMP_FPU: dump FPU register state, not just integer
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* @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state
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*/
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enum CPUDumpFlags {
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CPU_DUMP_CODE = 0x00010000,
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CPU_DUMP_FPU = 0x00020000,
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CPU_DUMP_CCOP = 0x00040000,
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};
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/**
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* cpu_dump_state:
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* @cpu: The CPU whose state is to be dumped.
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* @f: File to dump to.
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* @cpu_fprintf: Function to dump with.
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* @flags: Flags what to dump.
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*
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* Dumps CPU state.
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*/
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void cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
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int flags);
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/**
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* cpu_dump_statistics:
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* @cpu: The CPU whose state is to be dumped.
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* @f: File to dump to.
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* @cpu_fprintf: Function to dump with.
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* @flags: Flags what to dump.
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*
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* Dumps CPU statistics.
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*/
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void cpu_dump_statistics(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
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int flags);
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#ifndef CONFIG_USER_ONLY
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/**
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* cpu_get_phys_page_debug:
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* @cpu: The CPU to obtain the physical page address for.
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* @addr: The virtual address.
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*
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* Obtains the physical page corresponding to a virtual one.
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* Use it only for debugging because no protection checks are done.
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*
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* Returns: Corresponding physical page address or -1 if no page found.
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*/
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static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
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{
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CPUClass *cc = CPU_GET_CLASS(cpu);
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return cc->get_phys_page_debug(cpu, addr);
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}
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#endif
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/**
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* cpu_reset:
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* @cpu: The CPU whose state is to be reset.
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*/
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void cpu_reset(CPUState *cpu);
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/**
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* cpu_class_by_name:
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* @typename: The CPU base type.
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* @cpu_model: The model string without any parameters.
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*
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* Looks up a CPU #ObjectClass matching name @cpu_model.
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*
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* Returns: A #CPUClass or %NULL if not matching class is found.
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*/
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ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model);
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/**
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* qemu_cpu_has_work:
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* @cpu: The vCPU to check.
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*
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* Checks whether the CPU has work to do.
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*
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* Returns: %true if the CPU has work, %false otherwise.
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*/
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bool qemu_cpu_has_work(CPUState *cpu);
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/**
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* qemu_cpu_is_self:
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* @cpu: The vCPU to check against.
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*
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* Checks whether the caller is executing on the vCPU thread.
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*
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* Returns: %true if called from @cpu's thread, %false otherwise.
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*/
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bool qemu_cpu_is_self(CPUState *cpu);
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/**
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* qemu_cpu_kick:
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* @cpu: The vCPU to kick.
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*
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* Kicks @cpu's thread.
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*/
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void qemu_cpu_kick(CPUState *cpu);
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/**
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* cpu_is_stopped:
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* @cpu: The CPU to check.
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*
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* Checks whether the CPU is stopped.
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*
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* Returns: %true if run state is not running or if artificially stopped;
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* %false otherwise.
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*/
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bool cpu_is_stopped(CPUState *cpu);
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/**
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* run_on_cpu:
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* @cpu: The vCPU to run on.
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* @func: The function to be executed.
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* @data: Data to pass to the function.
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*
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* Schedules the function @func for execution on the vCPU @cpu.
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*/
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void run_on_cpu(CPUState *cpu, void (*func)(void *data), void *data);
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/**
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* async_run_on_cpu:
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* @cpu: The vCPU to run on.
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* @func: The function to be executed.
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* @data: Data to pass to the function.
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*
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* Schedules the function @func for execution on the vCPU @cpu asynchronously.
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*/
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void async_run_on_cpu(CPUState *cpu, void (*func)(void *data), void *data);
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/**
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* qemu_for_each_cpu:
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* @func: The function to be executed.
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* @data: Data to pass to the function.
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*
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* Executes @func for each CPU.
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*/
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void qemu_for_each_cpu(void (*func)(CPUState *cpu, void *data), void *data);
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/**
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* qemu_get_cpu:
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* @index: The CPUState@cpu_index value of the CPU to obtain.
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*
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* Gets a CPU matching @index.
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*
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* Returns: The CPU or %NULL if there is no matching CPU.
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*/
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CPUState *qemu_get_cpu(int index);
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/**
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* cpu_exists:
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* @id: Guest-exposed CPU ID to lookup.
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*
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* Search for CPU with specified ID.
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*
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* Returns: %true - CPU is found, %false - CPU isn't found.
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*/
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bool cpu_exists(int64_t id);
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#ifndef CONFIG_USER_ONLY
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typedef void (*CPUInterruptHandler)(CPUState *, int);
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extern CPUInterruptHandler cpu_interrupt_handler;
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/**
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* cpu_interrupt:
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* @cpu: The CPU to set an interrupt on.
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* @mask: The interupts to set.
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*
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* Invokes the interrupt handler.
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*/
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static inline void cpu_interrupt(CPUState *cpu, int mask)
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{
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cpu_interrupt_handler(cpu, mask);
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}
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#else /* USER_ONLY */
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void cpu_interrupt(CPUState *cpu, int mask);
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#endif /* USER_ONLY */
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#ifndef CONFIG_USER_ONLY
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static inline void cpu_unassigned_access(CPUState *cpu, hwaddr addr,
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bool is_write, bool is_exec,
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int opaque, unsigned size)
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{
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CPUClass *cc = CPU_GET_CLASS(cpu);
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if (cc->do_unassigned_access) {
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cc->do_unassigned_access(cpu, addr, is_write, is_exec, opaque, size);
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}
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}
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#endif
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/**
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* cpu_reset_interrupt:
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* @cpu: The CPU to clear the interrupt on.
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* @mask: The interrupt mask to clear.
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*
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* Resets interrupts on the vCPU @cpu.
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*/
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void cpu_reset_interrupt(CPUState *cpu, int mask);
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/**
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* cpu_exit:
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* @cpu: The CPU to exit.
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*
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* Requests the CPU @cpu to exit execution.
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*/
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void cpu_exit(CPUState *cpu);
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/**
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* cpu_resume:
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* @cpu: The CPU to resume.
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*
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* Resumes CPU, i.e. puts CPU into runnable state.
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*/
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void cpu_resume(CPUState *cpu);
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/**
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* qemu_init_vcpu:
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* @cpu: The vCPU to initialize.
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*
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* Initializes a vCPU.
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*/
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void qemu_init_vcpu(CPUState *cpu);
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#define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */
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#define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */
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#define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */
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/**
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* cpu_single_step:
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* @cpu: CPU to the flags for.
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* @enabled: Flags to enable.
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*
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* Enables or disables single-stepping for @cpu.
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*/
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void cpu_single_step(CPUState *cpu, int enabled);
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#ifdef CONFIG_SOFTMMU
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extern const struct VMStateDescription vmstate_cpu_common;
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#else
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#define vmstate_cpu_common vmstate_dummy
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#endif
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#define VMSTATE_CPU() { \
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.name = "parent_obj", \
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.size = sizeof(CPUState), \
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.vmsd = &vmstate_cpu_common, \
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.flags = VMS_STRUCT, \
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.offset = 0, \
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}
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|
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#endif
|