a0c9400a5b
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-3-gaosong@loongson.cn>
265 lines
7.3 KiB
C
265 lines
7.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* LoongArch emulation for QEMU - main translation routines.
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*
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* Copyright (c) 2021 Loongson Technology Corporation Limited
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "tcg/tcg-op.h"
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#include "exec/translator.h"
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#include "exec/helper-proto.h"
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#include "exec/helper-gen.h"
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#include "exec/log.h"
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#include "qemu/qemu-print.h"
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#include "fpu/softfloat.h"
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#include "translate.h"
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#include "internals.h"
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/* Global register indices */
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TCGv cpu_gpr[32], cpu_pc;
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static TCGv cpu_lladdr, cpu_llval;
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TCGv_i64 cpu_fpr[32];
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#include "exec/gen-icount.h"
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#define DISAS_STOP DISAS_TARGET_0
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#define DISAS_EXIT DISAS_TARGET_1
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#define DISAS_EXIT_UPDATE DISAS_TARGET_2
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static inline int plus_1(DisasContext *ctx, int x)
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{
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return x + 1;
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}
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static inline int shl_2(DisasContext *ctx, int x)
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{
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return x << 2;
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}
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/*
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* LoongArch the upper 32 bits are undefined ("can be any value").
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* QEMU chooses to nanbox, because it is most likely to show guest bugs early.
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*/
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static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in)
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{
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tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32));
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}
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void generate_exception(DisasContext *ctx, int excp)
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{
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tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
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gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
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ctx->base.is_jmp = DISAS_NORETURN;
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}
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static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
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{
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if (translator_use_goto_tb(&ctx->base, dest)) {
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tcg_gen_goto_tb(n);
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tcg_gen_movi_tl(cpu_pc, dest);
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tcg_gen_exit_tb(ctx->base.tb, n);
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} else {
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tcg_gen_movi_tl(cpu_pc, dest);
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tcg_gen_lookup_and_goto_ptr();
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}
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}
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static void loongarch_tr_init_disas_context(DisasContextBase *dcbase,
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CPUState *cs)
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{
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int64_t bound;
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DisasContext *ctx = container_of(dcbase, DisasContext, base);
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ctx->page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
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ctx->plv = ctx->base.tb->flags & HW_FLAGS_PLV_MASK;
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if (ctx->base.tb->flags & HW_FLAGS_CRMD_PG) {
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ctx->mem_idx = ctx->plv;
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} else {
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ctx->mem_idx = MMU_IDX_DA;
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}
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/* Bound the number of insns to execute to those left on the page. */
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bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
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ctx->base.max_insns = MIN(ctx->base.max_insns, bound);
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ctx->zero = tcg_constant_tl(0);
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}
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static void loongarch_tr_tb_start(DisasContextBase *dcbase, CPUState *cs)
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{
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}
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static void loongarch_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
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{
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DisasContext *ctx = container_of(dcbase, DisasContext, base);
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tcg_gen_insn_start(ctx->base.pc_next);
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}
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/*
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* Wrappers for getting reg values.
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*
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* The $zero register does not have cpu_gpr[0] allocated -- we supply the
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* constant zero as a source, and an uninitialized sink as destination.
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*
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* Further, we may provide an extension for word operations.
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*/
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static TCGv gpr_src(DisasContext *ctx, int reg_num, DisasExtend src_ext)
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{
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TCGv t;
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if (reg_num == 0) {
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return ctx->zero;
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}
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switch (src_ext) {
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case EXT_NONE:
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return cpu_gpr[reg_num];
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case EXT_SIGN:
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t = tcg_temp_new();
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tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]);
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return t;
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case EXT_ZERO:
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t = tcg_temp_new();
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tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]);
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return t;
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}
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g_assert_not_reached();
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}
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static TCGv gpr_dst(DisasContext *ctx, int reg_num, DisasExtend dst_ext)
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{
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if (reg_num == 0 || dst_ext) {
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return tcg_temp_new();
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}
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return cpu_gpr[reg_num];
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}
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static void gen_set_gpr(int reg_num, TCGv t, DisasExtend dst_ext)
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{
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if (reg_num != 0) {
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switch (dst_ext) {
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case EXT_NONE:
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tcg_gen_mov_tl(cpu_gpr[reg_num], t);
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break;
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case EXT_SIGN:
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tcg_gen_ext32s_tl(cpu_gpr[reg_num], t);
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break;
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case EXT_ZERO:
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tcg_gen_ext32u_tl(cpu_gpr[reg_num], t);
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break;
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default:
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g_assert_not_reached();
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}
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}
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}
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#include "decode-insns.c.inc"
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#include "insn_trans/trans_arith.c.inc"
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#include "insn_trans/trans_shift.c.inc"
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#include "insn_trans/trans_bit.c.inc"
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#include "insn_trans/trans_memory.c.inc"
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#include "insn_trans/trans_atomic.c.inc"
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#include "insn_trans/trans_extra.c.inc"
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#include "insn_trans/trans_farith.c.inc"
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#include "insn_trans/trans_fcmp.c.inc"
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#include "insn_trans/trans_fcnv.c.inc"
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#include "insn_trans/trans_fmov.c.inc"
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#include "insn_trans/trans_fmemory.c.inc"
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#include "insn_trans/trans_branch.c.inc"
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#include "insn_trans/trans_privileged.c.inc"
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#include "insn_trans/trans_lsx.c.inc"
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static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
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{
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CPULoongArchState *env = cs->env_ptr;
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DisasContext *ctx = container_of(dcbase, DisasContext, base);
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ctx->opcode = translator_ldl(env, &ctx->base, ctx->base.pc_next);
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if (!decode(ctx, ctx->opcode)) {
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qemu_log_mask(LOG_UNIMP, "Error: unknown opcode. "
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TARGET_FMT_lx ": 0x%x\n",
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ctx->base.pc_next, ctx->opcode);
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generate_exception(ctx, EXCCODE_INE);
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}
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ctx->base.pc_next += 4;
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}
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static void loongarch_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
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{
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DisasContext *ctx = container_of(dcbase, DisasContext, base);
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switch (ctx->base.is_jmp) {
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case DISAS_STOP:
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tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
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tcg_gen_lookup_and_goto_ptr();
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break;
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case DISAS_TOO_MANY:
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gen_goto_tb(ctx, 0, ctx->base.pc_next);
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break;
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case DISAS_NORETURN:
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break;
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case DISAS_EXIT_UPDATE:
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tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
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QEMU_FALLTHROUGH;
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case DISAS_EXIT:
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tcg_gen_exit_tb(NULL, 0);
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break;
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default:
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g_assert_not_reached();
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}
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}
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static void loongarch_tr_disas_log(const DisasContextBase *dcbase,
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CPUState *cpu, FILE *logfile)
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{
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qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
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target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size);
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}
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static const TranslatorOps loongarch_tr_ops = {
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.init_disas_context = loongarch_tr_init_disas_context,
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.tb_start = loongarch_tr_tb_start,
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.insn_start = loongarch_tr_insn_start,
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.translate_insn = loongarch_tr_translate_insn,
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.tb_stop = loongarch_tr_tb_stop,
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.disas_log = loongarch_tr_disas_log,
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};
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void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
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target_ulong pc, void *host_pc)
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{
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DisasContext ctx;
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translator_loop(cs, tb, max_insns, pc, host_pc,
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&loongarch_tr_ops, &ctx.base);
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}
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void loongarch_translate_init(void)
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{
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int i;
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cpu_gpr[0] = NULL;
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for (i = 1; i < 32; i++) {
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cpu_gpr[i] = tcg_global_mem_new(cpu_env,
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offsetof(CPULoongArchState, gpr[i]),
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regnames[i]);
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}
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for (i = 0; i < 32; i++) {
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int off = offsetof(CPULoongArchState, fpr[i]);
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cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, off, fregnames[i]);
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}
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cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPULoongArchState, pc), "pc");
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cpu_lladdr = tcg_global_mem_new(cpu_env,
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offsetof(CPULoongArchState, lladdr), "lladdr");
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cpu_llval = tcg_global_mem_new(cpu_env,
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offsetof(CPULoongArchState, llval), "llval");
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}
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