a022e0de53
It is easier to manage one array of MMIO MR rather than one per vCPU. Signed-off-by: Bibo Mao <maobibo@loongson.cn> [PMD: Extracted from bigger commit, added commit description] Co-Developed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Bibo Mao <maobibo@loongson.cn> Tested-by: Bibo Mao <maobibo@loongson.cn> Acked-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20240805180622.21001-6-philmd@linaro.org>
49 lines
1.0 KiB
C
49 lines
1.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Loongson ipi interrupt header files
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*
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* Copyright (C) 2021 Loongson Technology Corporation Limited
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*/
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#ifndef HW_LOONGSON_IPI_H
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#define HW_LOONGSON_IPI_H
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#include "qom/object.h"
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#include "hw/intc/loongson_ipi_common.h"
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#include "hw/sysbus.h"
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#define IPI_MBX_NUM 4
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#define TYPE_LOONGSON_IPI "loongson_ipi"
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OBJECT_DECLARE_TYPE(LoongsonIPIState, LoongsonIPIClass, LOONGSON_IPI)
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typedef struct IPICore {
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LoongsonIPIState *ipi;
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uint32_t status;
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uint32_t en;
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uint32_t set;
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uint32_t clear;
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/* 64bit buf divide into 2 32bit buf */
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uint32_t buf[IPI_MBX_NUM * 2];
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qemu_irq irq;
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} IPICore;
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struct LoongsonIPIClass {
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LoongsonIPICommonClass parent_class;
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DeviceRealize parent_realize;
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DeviceUnrealize parent_unrealize;
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};
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struct LoongsonIPIState {
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LoongsonIPICommonState parent_obj;
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MemoryRegion *ipi_mmio_mem;
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MemoryRegion ipi_iocsr_mem;
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MemoryRegion ipi64_iocsr_mem;
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uint32_t num_cpu;
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IPICore *cpu;
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};
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#endif
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