c2e6d7d8e7
QEMU populates the apic_state attribute of x86 CPUs if supported by real
hardware or if SMP is active. When handling interrupts, it just checks whether
apic_state is populated to route the interrupt to the PIC or to the APIC.
However, chapter 10.4.3 of [1] requires that:
When IA32_APIC_BASE[11] is 0, the processor is functionally equivalent to an
IA-32 processor without an on-chip APIC.
This means that when apic_state is populated, QEMU needs to check for the
MSR_IA32_APICBASE_ENABLE flag in addition. Implement this which fixes some
real-world BIOSes.
[1] Intel 64 and IA-32 Architectures Software Developer's Manual, Vol. 3A:
System Programming Guide, Part 1
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20240106132546.21248-3-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
29 lines
901 B
C
29 lines
901 B
C
#ifndef APIC_H
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#define APIC_H
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/* apic.c */
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void apic_set_max_apic_id(uint32_t max_apic_id);
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int apic_accept_pic_intr(DeviceState *s);
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void apic_deliver_pic_intr(DeviceState *s, int level);
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void apic_deliver_nmi(DeviceState *d);
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int apic_get_interrupt(DeviceState *s);
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int cpu_set_apic_base(DeviceState *s, uint64_t val);
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uint64_t cpu_get_apic_base(DeviceState *s);
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bool cpu_is_apic_enabled(DeviceState *s);
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void cpu_set_apic_tpr(DeviceState *s, uint8_t val);
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uint8_t cpu_get_apic_tpr(DeviceState *s);
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void apic_init_reset(DeviceState *s);
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void apic_sipi(DeviceState *s);
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void apic_poll_irq(DeviceState *d);
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void apic_designate_bsp(DeviceState *d, bool bsp);
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int apic_get_highest_priority_irr(DeviceState *dev);
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int apic_msr_read(int index, uint64_t *val);
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int apic_msr_write(int index, uint64_t val);
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bool is_x2apic_mode(DeviceState *d);
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/* pc.c */
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DeviceState *cpu_get_current_apic(void);
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#endif
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