qemu/hw/riscv
Markus Armbruster 9fc7fc4d39 qom: Less verbose object_initialize_child()
All users of object_initialize_child() pass the obvious child size
argument.  Almost all pass &error_abort and no properties.  Tiresome.

Rename object_initialize_child() to
object_initialize_child_with_props() to free the name.  New
convenience wrapper object_initialize_child() automates the size
argument, and passes &error_abort and no properties.

Rename object_initialize_childv() to
object_initialize_child_with_propsv() for consistency.

Convert callers with this Coccinelle script:

    @@
    expression parent, propname, type;
    expression child, size;
    symbol error_abort;
    @@
    -    object_initialize_child(parent, propname, OBJECT(child), size, type, &error_abort, NULL)
    +    object_initialize_child(parent, propname, child, size, type, &error_abort, NULL)

    @@
    expression parent, propname, type;
    expression child;
    symbol error_abort;
    @@
    -    object_initialize_child(parent, propname, child, sizeof(*child), type, &error_abort, NULL)
    +    object_initialize_child(parent, propname, child, type)

    @@
    expression parent, propname, type;
    expression child;
    symbol error_abort;
    @@
    -    object_initialize_child(parent, propname, &child, sizeof(child), type, &error_abort, NULL)
    +    object_initialize_child(parent, propname, &child, type)

    @@
    expression parent, propname, type;
    expression child, size, err;
    expression list props;
    @@
    -    object_initialize_child(parent, propname, child, size, type, err, props)
    +    object_initialize_child_with_props(parent, propname, child, size, type, err, props)

Note that Coccinelle chokes on ARMSSE typedef vs. macro in
hw/arm/armsse.c.  Worked around by temporarily renaming the macro for
the spatch run.

Signed-off-by: Markus Armbruster <armbru@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
[Rebased: machine opentitan is new (commit fe0fe4735e)]
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-37-armbru@redhat.com>
2020-06-15 22:05:28 +02:00
..
boot.c riscv: Change the default behavior if no -bios option is specified 2020-06-03 09:11:51 -07:00
Kconfig riscv: Initial commit of OpenTitan machine 2020-06-03 09:11:51 -07:00
Makefile.objs riscv: Initial commit of OpenTitan machine 2020-06-03 09:11:51 -07:00
opentitan.c qom: Less verbose object_initialize_child() 2020-06-15 22:05:28 +02:00
riscv_hart.c qom: Less verbose object_initialize_child() 2020-06-15 22:05:28 +02:00
riscv_htif.c chardev: Use QEMUChrEvent enum in IOEventHandler typedef 2020-01-08 11:15:35 +01:00
sifive_clint.c qdev: Convert uses of qdev_create() with Coccinelle 2020-06-15 22:00:10 +02:00
sifive_e_prci.c qdev: Convert uses of qdev_create() with Coccinelle 2020-06-15 22:00:10 +02:00
sifive_e.c qom: Less verbose object_initialize_child() 2020-06-15 22:05:28 +02:00
sifive_gpio.c Include migration/vmstate.h less 2019-08-16 13:31:52 +02:00
sifive_plic.c qdev: Convert uses of qdev_create() with Coccinelle 2020-06-15 22:00:10 +02:00
sifive_test.c qdev: Convert uses of qdev_create() with Coccinelle 2020-06-15 22:00:10 +02:00
sifive_u_otp.c qdev: set properties with device_class_set_props() 2020-01-24 20:59:15 +01:00
sifive_u_prci.c riscv: sifive: Implement PRCI model for FU540 2019-09-17 08:42:47 -07:00
sifive_u.c qom: Less verbose object_initialize_child() 2020-06-15 22:05:28 +02:00
sifive_uart.c chardev: Use QEMUChrEvent enum in IOEventHandler typedef 2020-01-08 11:15:35 +01:00
spike.c riscv: Fix to put "riscv.hart_array" devices on sysbus 2020-06-15 21:36:21 +02:00
trace-events SiFive RISC-V GPIO Device 2019-05-24 11:58:30 -07:00
virt.c qdev: Convert uses of qdev_create() manually 2020-06-15 22:05:08 +02:00