Peter Maydell 9f82e0ff4b target-arm: A64: Implement SIMD scalar indexed instructions ...

Implement the SIMD scalar indexed instructions. The encoding
here is nearly identical to the vector indexed grouping, so
we combine the two.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>

2014-02-20 10:35:49 +00:00

..

arm-semi.c

…

cpu64.c

target-arm: Switch ARMCPUInfo arrays to use terminator entries

2014-01-14 10:09:04 +10:00

cpu-qom.h

…

cpu.c

ARM: Convert MIDR to a property

2014-01-31 14:47:32 +00:00

cpu.h

target-arm: Move arm_rmode_to_sf to a shared location.

2014-01-31 14:47:33 +00:00

crypto_helper.c

…

gdbstub64.c

…

gdbstub.c

…

helper-a64.c

target-arm: A64: Implement plain vector SIMD indexed element insns

2014-02-20 10:35:48 +00:00

helper-a64.h

target-arm: A64: Implement plain vector SIMD indexed element insns

2014-02-20 10:35:48 +00:00

helper.c

exec: Make stl_*_phys input an AddressSpace

2014-02-11 22:57:18 +10:00

helper.h

target-arm: A64: Implement 2-reg-misc CNT, NOT and RBIT

2014-02-08 14:47:28 +00:00

iwmmxt_helper.c

…

kvm32.c

…

kvm64.c

…

kvm_arm.h

…

kvm-consts.h

…

kvm-stub.c

…

kvm.c

…

machine.c

…

Makefile.objs

…

neon_helper.c

target-arm: A64: Implement 2-reg-misc CNT, NOT and RBIT

2014-02-08 14:47:28 +00:00

op_addsub.h

…

op_helper.c

…

translate-a64.c

target-arm: A64: Implement SIMD scalar indexed instructions

2014-02-20 10:35:49 +00:00

translate.c

target-arm: Add support for AArch32 64bit VCVTB and VCVTT

2014-02-08 14:47:28 +00:00

translate.h

…