Frank Chang d2c1a177b1 target/riscv: rvb: add b-ext version cpu option ...

Default b-ext version is v0.93.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210505160620.15723-18-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

2021-06-08 09:59:46 +10:00

..

insn_trans

target/riscv: rvb: add/shift with prefix zero-extend

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arch_dump.c

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bitmanip_helper.c

target/riscv: rvb: generalized or-combine

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cpu_bits.h

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cpu_helper.c

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cpu_user.h

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cpu-param.h

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cpu.c

target/riscv: rvb: add b-ext version cpu option

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cpu.h

target/riscv: rvb: add b-ext version cpu option

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csr.c

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fpu_helper.c

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gdbstub.c

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helper.h

target/riscv: rvb: generalized or-combine

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insn16.decode

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insn32.decode

target/riscv: rvb: add/shift with prefix zero-extend

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instmap.h

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internals.h

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machine.c

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meson.build

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monitor.c

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op_helper.c

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pmp.c

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pmp.h

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trace-events

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trace.h

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translate.c

target/riscv: rvb: add/shift with prefix zero-extend

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vector_helper.c

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