qemu/target/arm
Peter Maydell 5b2c8af89b target/arm: Make WFI a NOP for userspace emulators
The WFI insn is not system-mode only, though it doesn't usually make
a huge amount of sense for userspace code to execute it.  Currently
if you try it in qemu-arm then the helper function will raise an
EXCP_HLT exception, which is not covered by the switch in cpu_loop()
and results in an abort:

qemu: unhandled CPU exception 0x10001 - aborting
R00=00000001 R01=408003e4 R02=408003ec R03=000102ec
R04=00010a28 R05=00010158 R06=00087460 R07=00010158
R08=00000000 R09=00000000 R10=00085b7c R11=408002a4
R12=408002b8 R13=408002a0 R14=0001057c R15=000102f8
PSR=60000010 -ZC- A usr32
qemu:handle_cpu_signal received signal outside vCPU context @ pc=0x7fcbfa4f0a12

Make the WFI helper function return immediately in the usermode
emulator. This turns WFI into a NOP, which is OK because:
 * architecturally "WFI is a NOP" is a permitted implementation
 * aarch64 Linux kernels use the SCTLR_EL1.nTWI bit to trap
   userspace WFI and NOP it (though aarch32 kernels currently
   just let WFI do whatever it would do)

We could in theory make the translate.c code special case user-mode
emulation and NOP the insn entirely rather than making the helper
do nothing, but because no real world code will be trying to
execute WFI we don't care about efficiency and the helper provides
a single place where we can make the change rather than having
to touch multiple places in translate.c and translate-a64.c.

Fixes: https://bugs.launchpad.net/qemu/+bug/1926759
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210430162212.825-1-peter.maydell@linaro.org
2021-05-10 13:24:09 +01:00
..
a32-uncond.decode
a32.decode
arch_dump.c
arm_ldst.h
arm-powerctl.c
arm-powerctl.h
cpu64.c Revert "target/arm: Make number of counters in PMCR follow the CPU" 2021-04-06 11:49:14 +01:00
cpu_tcg.c Revert "target/arm: Make number of counters in PMCR follow the CPU" 2021-04-06 11:49:14 +01:00
cpu-param.h linux-user/aarch64: Implement PR_TAGGED_ADDR_ENABLE 2021-02-16 13:06:16 +00:00
cpu-qom.h
cpu.c Do not include sysemu/sysemu.h if it's not really necessary 2021-05-02 17:24:50 +02:00
cpu.h target/arm: Add ALIGN_MEM to TBFLAG_ANY 2021-04-30 11:16:50 +01:00
crypto_helper.c
debug_helper.c
gdbstub64.c
gdbstub.c target/arm: use official org.gnu.gdb.aarch64.sve layout for registers 2021-01-18 10:05:06 +00:00
helper-a64.c target/arm: Add wrapper macros for accessing tbflags 2021-04-30 11:16:50 +01:00
helper-a64.h target/arm: Merge mte_check1, mte_checkN 2021-04-30 11:16:49 +01:00
helper-sve.h
helper.c target/arm: Fix tlbbits calculation in tlbi_aa64_vae2is_write() 2021-05-10 13:24:09 +01:00
helper.h
idau.h
internals.h target/arm: Rename mte_probe1 to mte_probe 2021-04-30 11:16:49 +01:00
iwmmxt_helper.c
kvm64.c Revert "target/arm: Make number of counters in PMCR follow the CPU" 2021-04-06 11:49:14 +01:00
kvm_arm.h hw/arm/virt: KVM: The IPA lower bound is 32 2021-03-12 12:47:11 +00:00
kvm-consts.h
kvm-stub.c
kvm.c hw/arm/virt: KVM: The IPA lower bound is 32 2021-03-12 12:47:11 +00:00
m_helper.c semihosting: Move include/hw/semihosting/ -> include/semihosting/ 2021-03-10 15:34:12 +00:00
m-nocp.decode target/arm: Implement new v8.1M VLLDM and VLSTM encodings 2020-12-10 11:44:56 +00:00
machine.c target/arm: Don't migrate CPUARMState.features 2021-02-11 11:50:13 +00:00
meson.build target/arm: Make translate-neon.c.inc its own compilation unit 2021-05-10 13:24:09 +01:00
monitor.c target/arm: Add cpu properties to control pauth 2021-01-19 14:38:51 +00:00
mte_helper.c target/arm: Rename mte_probe1 to mte_probe 2021-04-30 11:16:49 +01:00
neon_helper.c
neon-dp.decode
neon-ls.decode target/arm: Fix decode of align in VLDST_single 2021-04-30 11:16:49 +01:00
neon-shared.decode
op_addsub.h
op_helper.c target/arm: Make WFI a NOP for userspace emulators 2021-05-10 13:24:09 +01:00
pauth_helper.c target/arm: Implement an IMPDEF pauth algorithm 2021-01-19 14:38:51 +00:00
psci.c
sve_helper.c target/arm: Simplify sve mte checking 2021-04-30 11:16:49 +01:00
sve.decode
syndrome.h target/arm: Split out syndrome.h from internals.h 2021-02-16 13:16:18 +00:00
t16.decode
t32.decode target/arm: Implement M-profile "minimal RAS implementation" 2020-12-10 11:44:56 +00:00
tlb_helper.c target/arm: Set ARMMMUFaultInfo.level in user-only arm_cpu_tlb_fill 2021-03-23 14:07:55 +00:00
trace-events
trace.h
translate-a32.h target/arm: Make translate-neon.c.inc its own compilation unit 2021-05-10 13:24:09 +01:00
translate-a64.c target/arm: Share unallocated_encoding() and gen_exception_insn() 2021-05-10 13:24:09 +01:00
translate-a64.h target/arm: Share unallocated_encoding() and gen_exception_insn() 2021-05-10 13:24:09 +01:00
translate-m-nocp.c target/arm: Split m-nocp trans functions into their own file 2021-05-10 13:24:09 +01:00
translate-neon.c target/arm: Make translate-neon.c.inc its own compilation unit 2021-05-10 13:24:09 +01:00
translate-sve.c target/arm: Enforce alignment for sve LD1R 2021-04-30 11:16:51 +01:00
translate-vfp.c target/arm: Make translate-vfp.c.inc its own compilation unit 2021-05-10 13:24:09 +01:00
translate.c target/arm: Make translate-neon.c.inc its own compilation unit 2021-05-10 13:24:09 +01:00
translate.h target/arm: Move NeonGenThreeOpEnvFn typedef to translate.h 2021-05-10 13:24:09 +01:00
vec_helper.c target/arm: Speed up aarch64 TBL/TBX 2021-03-05 15:17:34 +00:00
vec_internal.h
vfp_helper.c
vfp-uncond.decode
vfp.decode target/arm: Implement VLDR/VSTR system register 2020-12-10 11:44:55 +00:00