163e5fa38e
**** Changes in v3 ****
Fix bugs exposed by dpmpyss_rnd_s0 instruction
Set correct size/signedness for constants
Test cases added to tests/tcg/hexagon/misc.c
**** Changes in v2 ****
Fix bug in imm_print identified in clang build
Currently, idef-parser skips all floating point instructions. However,
there are some floating point instructions that can be handled.
The following instructions are now parsed
F2_sfimm_p
F2_sfimm_n
F2_dfimm_p
F2_dfimm_n
F2_dfmpyll
F2_dfmpylh
To make these instructions work, we fix some bugs in parser-helpers.c
gen_rvalue_extend
gen_cast_op
imm_print
lexer properly sets size/signedness of constants
Test cases added to tests/tcg/hexagon/fpstuff.c
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Tested-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230501203125.4025991-1-tsimpson@quicinc.com>
575 lines
14 KiB
C
575 lines
14 KiB
C
/*
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* Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdio.h>
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#include <string.h>
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#define CORE_HAS_CABAC (__HEXAGON_ARCH__ <= 71)
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typedef unsigned char uint8_t;
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typedef unsigned short uint16_t;
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typedef unsigned int uint32_t;
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typedef unsigned long long uint64_t;
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static inline void S4_storerhnew_rr(void *p, int index, uint16_t v)
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{
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asm volatile("{\n\t"
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" r0 = %0\n\n"
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" memh(%1+%2<<#2) = r0.new\n\t"
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"}\n"
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:: "r"(v), "r"(p), "r"(index)
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: "r0", "memory");
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}
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static uint32_t data;
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static inline void *S4_storerbnew_ap(uint8_t v)
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{
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void *ret;
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asm volatile("{\n\t"
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" r0 = %1\n\n"
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" memb(%0 = ##data) = r0.new\n\t"
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"}\n"
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: "=r"(ret)
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: "r"(v)
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: "r0", "memory");
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return ret;
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}
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static inline void *S4_storerhnew_ap(uint16_t v)
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{
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void *ret;
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asm volatile("{\n\t"
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" r0 = %1\n\n"
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" memh(%0 = ##data) = r0.new\n\t"
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"}\n"
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: "=r"(ret)
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: "r"(v)
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: "r0", "memory");
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return ret;
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}
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static inline void *S4_storerinew_ap(uint32_t v)
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{
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void *ret;
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asm volatile("{\n\t"
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" r0 = %1\n\n"
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" memw(%0 = ##data) = r0.new\n\t"
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"}\n"
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: "=r"(ret)
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: "r"(v)
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: "r0", "memory");
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return ret;
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}
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static inline void S4_storeirbt_io(void *p, int pred)
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{
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asm volatile("p0 = cmp.eq(%0, #1)\n\t"
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"if (p0) memb(%1+#4)=#27\n\t"
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:: "r"(pred), "r"(p)
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: "p0", "memory");
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}
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static inline void S4_storeirbf_io(void *p, int pred)
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{
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asm volatile("p0 = cmp.eq(%0, #1)\n\t"
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"if (!p0) memb(%1+#4)=#27\n\t"
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:: "r"(pred), "r"(p)
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: "p0", "memory");
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}
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static inline void S4_storeirbtnew_io(void *p, int pred)
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{
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asm volatile("{\n\t"
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" p0 = cmp.eq(%0, #1)\n\t"
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" if (p0.new) memb(%1+#4)=#27\n\t"
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"}\n\t"
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:: "r"(pred), "r"(p)
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: "p0", "memory");
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}
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static inline void S4_storeirbfnew_io(void *p, int pred)
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{
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asm volatile("{\n\t"
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" p0 = cmp.eq(%0, #1)\n\t"
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" if (!p0.new) memb(%1+#4)=#27\n\t"
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"}\n\t"
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:: "r"(pred), "r"(p)
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: "p0", "memory");
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}
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static inline void S4_storeirht_io(void *p, int pred)
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{
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asm volatile("p0 = cmp.eq(%0, #1)\n\t"
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"if (p0) memh(%1+#4)=#27\n\t"
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:: "r"(pred), "r"(p)
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: "p0", "memory");
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}
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static inline void S4_storeirhf_io(void *p, int pred)
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{
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asm volatile("p0 = cmp.eq(%0, #1)\n\t"
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"if (!p0) memh(%1+#4)=#27\n\t"
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:: "r"(pred), "r"(p)
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: "p0", "memory");
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}
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static inline void S4_storeirhtnew_io(void *p, int pred)
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{
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asm volatile("{\n\t"
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" p0 = cmp.eq(%0, #1)\n\t"
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" if (p0.new) memh(%1+#4)=#27\n\t"
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"}\n\t"
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:: "r"(pred), "r"(p)
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: "p0", "memory");
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}
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static inline void S4_storeirhfnew_io(void *p, int pred)
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{
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asm volatile("{\n\t"
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" p0 = cmp.eq(%0, #1)\n\t"
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" if (!p0.new) memh(%1+#4)=#27\n\t"
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"}\n\t"
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:: "r"(pred), "r"(p)
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: "p0", "memory");
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}
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static inline void S4_storeirit_io(void *p, int pred)
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{
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asm volatile("p0 = cmp.eq(%0, #1)\n\t"
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"if (p0) memw(%1+#4)=#27\n\t"
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:: "r"(pred), "r"(p)
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: "p0", "memory");
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}
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static inline void S4_storeirif_io(void *p, int pred)
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{
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asm volatile("p0 = cmp.eq(%0, #1)\n\t"
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"if (!p0) memw(%1+#4)=#27\n\t"
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:: "r"(pred), "r"(p)
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: "p0", "memory");
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}
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static inline void S4_storeiritnew_io(void *p, int pred)
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{
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asm volatile("{\n\t"
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" p0 = cmp.eq(%0, #1)\n\t"
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" if (p0.new) memw(%1+#4)=#27\n\t"
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"}\n\t"
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:: "r"(pred), "r"(p)
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: "p0", "memory");
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}
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static inline void S4_storeirifnew_io(void *p, int pred)
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{
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asm volatile("{\n\t"
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" p0 = cmp.eq(%0, #1)\n\t"
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" if (!p0.new) memw(%1+#4)=#27\n\t"
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"}\n\t"
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:: "r"(pred), "r"(p)
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: "p0", "memory");
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}
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static int L2_ploadrifnew_pi(void *p, int pred)
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{
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int result;
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asm volatile("%0 = #31\n\t"
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"{\n\t"
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" p0 = cmp.eq(%2, #1)\n\t"
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" if (!p0.new) %0 = memw(%1++#4)\n\t"
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"}\n\t"
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: "=&r"(result), "+r"(p) : "r"(pred)
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: "p0");
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return result;
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}
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/*
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* Test that compound-compare-jump is executed in 2 parts
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* First we have to do all the compares in the packet and
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* account for auto-anding. Then, we can do the predicated
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* jump.
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*/
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static inline int cmpnd_cmp_jump(void)
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{
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int retval;
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asm ("r5 = #7\n\t"
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"r6 = #9\n\t"
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"{\n\t"
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" p0 = cmp.eq(r5, #7)\n\t"
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" if (p0.new) jump:nt 1f\n\t"
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" p0 = cmp.eq(r6, #7)\n\t"
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"}\n\t"
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"%0 = #12\n\t"
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"jump 2f\n\t"
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"1:\n\t"
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"%0 = #13\n\t"
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"2:\n\t"
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: "=r"(retval) :: "r5", "r6", "p0");
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return retval;
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}
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static inline int test_clrtnew(int arg1, int old_val)
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{
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int ret;
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asm volatile("r5 = %2\n\t"
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"{\n\t"
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"p0 = cmp.eq(%1, #1)\n\t"
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"if (p0.new) r5=#0\n\t"
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"}\n\t"
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"%0 = r5\n\t"
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: "=r"(ret)
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: "r"(arg1), "r"(old_val)
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: "p0", "r5");
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return ret;
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}
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int err;
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static void check(int val, int expect)
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{
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if (val != expect) {
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printf("ERROR: 0x%04x != 0x%04x\n", val, expect);
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err++;
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}
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}
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#if CORE_HAS_CABAC
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static void check64(long long val, long long expect)
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{
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if (val != expect) {
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printf("ERROR: 0x%016llx != 0x%016llx\n", val, expect);
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err++;
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}
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}
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#endif
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uint32_t init[10] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 };
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uint32_t array[10];
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uint32_t early_exit;
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/*
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* Write this as a function because we can't guarantee the compiler will
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* allocate a frame with just the SL2_return_tnew packet.
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*/
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static void SL2_return_tnew(int x);
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asm ("SL2_return_tnew:\n\t"
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" allocframe(#0)\n\t"
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" r1 = #1\n\t"
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" memw(##early_exit) = r1\n\t"
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" {\n\t"
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" p0 = cmp.eq(r0, #1)\n\t"
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" if (p0.new) dealloc_return:nt\n\t" /* SL2_return_tnew */
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" }\n\t"
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" r1 = #0\n\t"
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" memw(##early_exit) = r1\n\t"
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" dealloc_return\n\t"
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);
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static long long creg_pair(int x, int y)
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{
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long long retval;
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asm ("m0 = %1\n\t"
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"m1 = %2\n\t"
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"%0 = c7:6\n\t"
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: "=r"(retval) : "r"(x), "r"(y) : "m0", "m1");
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return retval;
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}
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#if CORE_HAS_CABAC
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static long long decbin(long long x, long long y, int *pred)
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{
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long long retval;
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asm ("%0 = decbin(%2, %3)\n\t"
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"%1 = p0\n\t"
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: "=r"(retval), "=r"(*pred)
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: "r"(x), "r"(y));
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return retval;
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}
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#endif
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/* Check that predicates are auto-and'ed in a packet */
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static int auto_and(void)
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{
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int retval;
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asm ("r5 = #1\n\t"
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"{\n\t"
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" p0 = cmp.eq(r1, #1)\n\t"
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" p0 = cmp.eq(r1, #2)\n\t"
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"}\n\t"
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"%0 = p0\n\t"
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: "=r"(retval)
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:
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: "r5", "p0");
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return retval;
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}
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void test_lsbnew(void)
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{
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int result;
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asm("r0 = #2\n\t"
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"r1 = #5\n\t"
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"{\n\t"
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" p0 = r0\n\t"
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" if (p0.new) r1 = #3\n\t"
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"}\n\t"
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"%0 = r1\n\t"
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: "=r"(result) :: "r0", "r1", "p0");
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check(result, 5);
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}
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void test_l2fetch(void)
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{
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/* These don't do anything in qemu, just make sure they don't assert */
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asm volatile ("l2fetch(r0, r1)\n\t"
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"l2fetch(r0, r3:2)\n\t");
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}
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static inline int ct0(uint32_t x)
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{
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int res;
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asm("%0 = ct0(%1)\n\t" : "=r"(res) : "r"(x));
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return res;
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}
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static inline int ct1(uint32_t x)
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{
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int res;
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asm("%0 = ct1(%1)\n\t" : "=r"(res) : "r"(x));
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return res;
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}
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static inline int ct0p(uint64_t x)
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{
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int res;
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asm("%0 = ct0(%1)\n\t" : "=r"(res) : "r"(x));
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return res;
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}
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static inline int ct1p(uint64_t x)
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{
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int res;
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asm("%0 = ct1(%1)\n\t" : "=r"(res) : "r"(x));
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return res;
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}
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void test_count_trailing_zeros_ones(void)
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{
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check(ct0(0x0000000f), 0);
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check(ct0(0x00000000), 32);
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check(ct0(0x000000f0), 4);
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check(ct1(0x000000f0), 0);
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check(ct1(0x0000000f), 4);
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check(ct1(0x00000000), 0);
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check(ct1(0xffffffff), 32);
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check(ct0p(0x000000000000000fULL), 0);
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check(ct0p(0x0000000000000000ULL), 64);
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check(ct0p(0x00000000000000f0ULL), 4);
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check(ct1p(0x00000000000000f0ULL), 0);
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check(ct1p(0x000000000000000fULL), 4);
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check(ct1p(0x0000000000000000ULL), 0);
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check(ct1p(0xffffffffffffffffULL), 64);
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check(ct1p(0xffffffffff0fffffULL), 20);
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check(ct1p(0xffffff0fffffffffULL), 36);
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}
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static inline int dpmpyss_rnd_s0(int x, int y)
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{
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int res;
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asm("%0 = mpy(%1, %2):rnd\n\t" : "=r"(res) : "r"(x), "r"(y));
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return res;
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}
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void test_dpmpyss_rnd_s0(void)
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{
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check(dpmpyss_rnd_s0(-1, 0x80000000), 1);
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check(dpmpyss_rnd_s0(0, 0x80000000), 0);
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check(dpmpyss_rnd_s0(1, 0x80000000), 0);
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check(dpmpyss_rnd_s0(0x7fffffff, 0x80000000), 0xc0000001);
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check(dpmpyss_rnd_s0(0x80000000, -1), 1);
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check(dpmpyss_rnd_s0(-1, -1), 0);
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check(dpmpyss_rnd_s0(0, -1), 0);
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check(dpmpyss_rnd_s0(1, -1), 0);
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check(dpmpyss_rnd_s0(0x7fffffff, -1), 0);
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check(dpmpyss_rnd_s0(0x80000000, 0), 0);
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check(dpmpyss_rnd_s0(-1, 0), 0);
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check(dpmpyss_rnd_s0(0, 0), 0);
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check(dpmpyss_rnd_s0(1, 0), 0);
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check(dpmpyss_rnd_s0(-1, -1), 0);
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check(dpmpyss_rnd_s0(0, -1), 0);
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check(dpmpyss_rnd_s0(1, -1), 0);
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check(dpmpyss_rnd_s0(0x7fffffff, 1), 0);
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check(dpmpyss_rnd_s0(0x80000000, 0x7fffffff), 0xc0000001);
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check(dpmpyss_rnd_s0(-1, 0x7fffffff), 0);
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check(dpmpyss_rnd_s0(0, 0x7fffffff), 0);
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check(dpmpyss_rnd_s0(1, 0x7fffffff), 0);
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check(dpmpyss_rnd_s0(0x7fffffff, 0x7fffffff), 0x3fffffff);
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}
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int main()
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{
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int res;
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#if CORE_HAS_CABAC
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long long res64;
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int pred;
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#endif
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memcpy(array, init, sizeof(array));
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S4_storerhnew_rr(array, 4, 0xffff);
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check(array[4], 0xffff);
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data = ~0;
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check((uint32_t)S4_storerbnew_ap(0x12), (uint32_t)&data);
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check(data, 0xffffff12);
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data = ~0;
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check((uint32_t)S4_storerhnew_ap(0x1234), (uint32_t)&data);
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check(data, 0xffff1234);
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data = ~0;
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check((uint32_t)S4_storerinew_ap(0x12345678), (uint32_t)&data);
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check(data, 0x12345678);
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/* Byte */
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memcpy(array, init, sizeof(array));
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S4_storeirbt_io(&array[1], 1);
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check(array[2], 27);
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S4_storeirbt_io(&array[2], 0);
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check(array[3], 3);
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memcpy(array, init, sizeof(array));
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S4_storeirbf_io(&array[3], 0);
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check(array[4], 27);
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S4_storeirbf_io(&array[4], 1);
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check(array[5], 5);
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memcpy(array, init, sizeof(array));
|
|
S4_storeirbtnew_io(&array[5], 1);
|
|
check(array[6], 27);
|
|
S4_storeirbtnew_io(&array[6], 0);
|
|
check(array[7], 7);
|
|
|
|
memcpy(array, init, sizeof(array));
|
|
S4_storeirbfnew_io(&array[7], 0);
|
|
check(array[8], 27);
|
|
S4_storeirbfnew_io(&array[8], 1);
|
|
check(array[9], 9);
|
|
|
|
/* Half word */
|
|
memcpy(array, init, sizeof(array));
|
|
S4_storeirht_io(&array[1], 1);
|
|
check(array[2], 27);
|
|
S4_storeirht_io(&array[2], 0);
|
|
check(array[3], 3);
|
|
|
|
memcpy(array, init, sizeof(array));
|
|
S4_storeirhf_io(&array[3], 0);
|
|
check(array[4], 27);
|
|
S4_storeirhf_io(&array[4], 1);
|
|
check(array[5], 5);
|
|
|
|
memcpy(array, init, sizeof(array));
|
|
S4_storeirhtnew_io(&array[5], 1);
|
|
check(array[6], 27);
|
|
S4_storeirhtnew_io(&array[6], 0);
|
|
check(array[7], 7);
|
|
|
|
memcpy(array, init, sizeof(array));
|
|
S4_storeirhfnew_io(&array[7], 0);
|
|
check(array[8], 27);
|
|
S4_storeirhfnew_io(&array[8], 1);
|
|
check(array[9], 9);
|
|
|
|
/* Word */
|
|
memcpy(array, init, sizeof(array));
|
|
S4_storeirit_io(&array[1], 1);
|
|
check(array[2], 27);
|
|
S4_storeirit_io(&array[2], 0);
|
|
check(array[3], 3);
|
|
|
|
memcpy(array, init, sizeof(array));
|
|
S4_storeirif_io(&array[3], 0);
|
|
check(array[4], 27);
|
|
S4_storeirif_io(&array[4], 1);
|
|
check(array[5], 5);
|
|
|
|
memcpy(array, init, sizeof(array));
|
|
S4_storeiritnew_io(&array[5], 1);
|
|
check(array[6], 27);
|
|
S4_storeiritnew_io(&array[6], 0);
|
|
check(array[7], 7);
|
|
|
|
memcpy(array, init, sizeof(array));
|
|
S4_storeirifnew_io(&array[7], 0);
|
|
check(array[8], 27);
|
|
S4_storeirifnew_io(&array[8], 1);
|
|
check(array[9], 9);
|
|
|
|
memcpy(array, init, sizeof(array));
|
|
res = L2_ploadrifnew_pi(&array[6], 0);
|
|
check(res, 6);
|
|
res = L2_ploadrifnew_pi(&array[7], 1);
|
|
check(res, 31);
|
|
|
|
int x = cmpnd_cmp_jump();
|
|
check(x, 12);
|
|
|
|
SL2_return_tnew(0);
|
|
check(early_exit, 0);
|
|
SL2_return_tnew(1);
|
|
check(early_exit, 1);
|
|
|
|
long long pair = creg_pair(5, 7);
|
|
check((int)pair, 5);
|
|
check((int)(pair >> 32), 7);
|
|
|
|
res = test_clrtnew(1, 7);
|
|
check(res, 0);
|
|
res = test_clrtnew(2, 7);
|
|
check(res, 7);
|
|
|
|
#if CORE_HAS_CABAC
|
|
res64 = decbin(0xf0f1f2f3f4f5f6f7LL, 0x7f6f5f4f3f2f1f0fLL, &pred);
|
|
check64(res64, 0x357980003700010cLL);
|
|
check(pred, 0);
|
|
|
|
res64 = decbin(0xfLL, 0x1bLL, &pred);
|
|
check64(res64, 0x78000100LL);
|
|
check(pred, 1);
|
|
#else
|
|
puts("Skipping cabac tests");
|
|
#endif
|
|
|
|
res = auto_and();
|
|
check(res, 0);
|
|
|
|
test_lsbnew();
|
|
|
|
test_l2fetch();
|
|
|
|
test_count_trailing_zeros_ones();
|
|
|
|
test_dpmpyss_rnd_s0();
|
|
|
|
puts(err ? "FAIL" : "PASS");
|
|
return err;
|
|
}
|