9e61bde56a
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1620 c046a42c-6fe2-441c-8c8c-71466251a162
525 lines
13 KiB
C
525 lines
13 KiB
C
/*
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* QEMU ESP emulation
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*
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* Copyright (c) 2005 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h"
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/* debug ESP card */
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//#define DEBUG_ESP
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#ifdef DEBUG_ESP
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#define DPRINTF(fmt, args...) \
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do { printf("ESP: " fmt , ##args); } while (0)
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#define pic_set_irq(irq, level) \
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do { printf("ESP: set_irq(%d): %d\n", (irq), (level)); pic_set_irq((irq),(level));} while (0)
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#else
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#define DPRINTF(fmt, args...)
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#endif
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#define ESPDMA_REGS 4
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#define ESPDMA_MAXADDR (ESPDMA_REGS * 4 - 1)
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#define ESP_MAXREG 0x3f
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#define TI_BUFSZ 65536
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#define DMA_VER 0xa0000000
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#define DMA_INTR 1
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#define DMA_INTREN 0x10
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#define DMA_LOADED 0x04000000
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typedef struct ESPState {
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BlockDriverState **bd;
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uint8_t rregs[ESP_MAXREG];
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uint8_t wregs[ESP_MAXREG];
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int irq;
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uint32_t espdmaregs[ESPDMA_REGS];
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uint32_t ti_size;
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uint32_t ti_rptr, ti_wptr;
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int ti_dir;
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uint8_t ti_buf[TI_BUFSZ];
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int dma;
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} ESPState;
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#define STAT_DO 0x00
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#define STAT_DI 0x01
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#define STAT_CD 0x02
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#define STAT_ST 0x03
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#define STAT_MI 0x06
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#define STAT_MO 0x07
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#define STAT_TC 0x10
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#define STAT_IN 0x80
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#define INTR_FC 0x08
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#define INTR_BS 0x10
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#define INTR_DC 0x20
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#define INTR_RST 0x80
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#define SEQ_0 0x0
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#define SEQ_CD 0x4
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static void handle_satn(ESPState *s)
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{
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uint8_t buf[32];
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uint32_t dmaptr, dmalen;
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unsigned int i;
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int64_t nb_sectors;
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int target;
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dmalen = s->wregs[0] | (s->wregs[1] << 8);
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target = s->wregs[4] & 7;
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DPRINTF("Select with ATN len %d target %d\n", dmalen, target);
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if (s->dma) {
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dmaptr = iommu_translate(s->espdmaregs[1]);
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DPRINTF("DMA Direction: %c, addr 0x%8.8x\n", s->espdmaregs[0] & 0x100? 'w': 'r', dmaptr);
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cpu_physical_memory_read(dmaptr, buf, dmalen);
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} else {
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buf[0] = 0;
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memcpy(&buf[1], s->ti_buf, dmalen);
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dmalen++;
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}
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for (i = 0; i < dmalen; i++) {
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DPRINTF("Command %2.2x\n", buf[i]);
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}
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s->ti_dir = 0;
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s->ti_size = 0;
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s->ti_rptr = 0;
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s->ti_wptr = 0;
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if (target >= 4 || !s->bd[target]) { // No such drive
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s->rregs[4] = STAT_IN;
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s->rregs[5] = INTR_DC;
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s->rregs[6] = SEQ_0;
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s->espdmaregs[0] |= DMA_INTR;
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pic_set_irq(s->irq, 1);
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return;
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}
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switch (buf[1]) {
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case 0x0:
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DPRINTF("Test Unit Ready (len %d)\n", buf[5]);
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break;
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case 0x12:
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DPRINTF("Inquiry (len %d)\n", buf[5]);
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memset(s->ti_buf, 0, 36);
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if (bdrv_get_type_hint(s->bd[target]) == BDRV_TYPE_CDROM) {
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s->ti_buf[0] = 5;
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memcpy(&s->ti_buf[16], "QEMU CDROM ", 16);
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} else {
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s->ti_buf[0] = 0;
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memcpy(&s->ti_buf[16], "QEMU HARDDISK ", 16);
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}
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memcpy(&s->ti_buf[8], "QEMU ", 8);
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s->ti_buf[2] = 1;
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s->ti_buf[3] = 2;
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s->ti_dir = 1;
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s->ti_size = 36;
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break;
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case 0x1a:
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DPRINTF("Mode Sense(6) (page %d, len %d)\n", buf[3], buf[5]);
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break;
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case 0x25:
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DPRINTF("Read Capacity (len %d)\n", buf[5]);
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memset(s->ti_buf, 0, 8);
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bdrv_get_geometry(s->bd[target], &nb_sectors);
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s->ti_buf[0] = (nb_sectors >> 24) & 0xff;
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s->ti_buf[1] = (nb_sectors >> 16) & 0xff;
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s->ti_buf[2] = (nb_sectors >> 8) & 0xff;
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s->ti_buf[3] = nb_sectors & 0xff;
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s->ti_buf[4] = 0;
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s->ti_buf[5] = 0;
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if (bdrv_get_type_hint(s->bd[target]) == BDRV_TYPE_CDROM)
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s->ti_buf[6] = 8; // sector size 2048
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else
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s->ti_buf[6] = 2; // sector size 512
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s->ti_buf[7] = 0;
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s->ti_dir = 1;
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s->ti_size = 8;
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break;
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case 0x28:
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{
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int64_t offset, len;
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if (bdrv_get_type_hint(s->bd[target]) == BDRV_TYPE_CDROM) {
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offset = ((buf[3] << 24) | (buf[4] << 16) | (buf[5] << 8) | buf[6]) * 4;
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len = ((buf[8] << 8) | buf[9]) * 4;
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s->ti_size = len * 2048;
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} else {
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offset = (buf[3] << 24) | (buf[4] << 16) | (buf[5] << 8) | buf[6];
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len = (buf[8] << 8) | buf[9];
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s->ti_size = len * 512;
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}
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DPRINTF("Read (10) (offset %lld len %lld)\n", offset, len);
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bdrv_read(s->bd[target], offset, s->ti_buf, len);
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// XXX error handling
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s->ti_dir = 1;
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break;
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}
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case 0x2a:
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{
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int64_t offset, len;
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if (bdrv_get_type_hint(s->bd[target]) == BDRV_TYPE_CDROM) {
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offset = ((buf[3] << 24) | (buf[4] << 16) | (buf[5] << 8) | buf[6]) * 4;
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len = ((buf[8] << 8) | buf[9]) * 4;
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s->ti_size = len * 2048;
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} else {
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offset = (buf[3] << 24) | (buf[4] << 16) | (buf[5] << 8) | buf[6];
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len = (buf[8] << 8) | buf[9];
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s->ti_size = len * 512;
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}
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DPRINTF("Write (10) (offset %lld len %lld)\n", offset, len);
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bdrv_write(s->bd[target], offset, s->ti_buf, len);
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// XXX error handling
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s->ti_dir = 0;
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break;
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}
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default:
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DPRINTF("Unknown SCSI command (%2.2x)\n", buf[1]);
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break;
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}
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s->rregs[4] = STAT_IN | STAT_TC | STAT_DI;
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s->rregs[5] = INTR_BS | INTR_FC;
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s->rregs[6] = SEQ_CD;
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s->espdmaregs[0] |= DMA_INTR;
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pic_set_irq(s->irq, 1);
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}
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static void dma_write(ESPState *s, const uint8_t *buf, uint32_t len)
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{
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uint32_t dmaptr, dmalen;
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dmalen = s->wregs[0] | (s->wregs[1] << 8);
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DPRINTF("Transfer status len %d\n", dmalen);
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if (s->dma) {
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dmaptr = iommu_translate(s->espdmaregs[1]);
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DPRINTF("DMA Direction: %c\n", s->espdmaregs[0] & 0x100? 'w': 'r');
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cpu_physical_memory_write(dmaptr, buf, len);
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s->rregs[4] = STAT_IN | STAT_TC | STAT_ST;
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s->rregs[5] = INTR_BS | INTR_FC;
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s->rregs[6] = SEQ_CD;
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} else {
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memcpy(s->ti_buf, buf, len);
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s->ti_size = dmalen;
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s->ti_rptr = 0;
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s->ti_wptr = 0;
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s->rregs[7] = dmalen;
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}
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s->espdmaregs[0] |= DMA_INTR;
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pic_set_irq(s->irq, 1);
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}
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static const uint8_t okbuf[] = {0, 0};
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static void handle_ti(ESPState *s)
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{
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uint32_t dmaptr, dmalen;
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unsigned int i;
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dmalen = s->wregs[0] | (s->wregs[1] << 8);
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DPRINTF("Transfer Information len %d\n", dmalen);
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if (s->dma) {
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dmaptr = iommu_translate(s->espdmaregs[1]);
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DPRINTF("DMA Direction: %c, addr 0x%8.8x\n", s->espdmaregs[0] & 0x100? 'w': 'r', dmaptr);
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for (i = 0; i < s->ti_size; i++) {
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dmaptr = iommu_translate(s->espdmaregs[1] + i);
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if (s->ti_dir)
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cpu_physical_memory_write(dmaptr, &s->ti_buf[i], 1);
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else
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cpu_physical_memory_read(dmaptr, &s->ti_buf[i], 1);
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}
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s->rregs[4] = STAT_IN | STAT_TC | STAT_ST;
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s->rregs[5] = INTR_BS;
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s->rregs[6] = 0;
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s->espdmaregs[0] |= DMA_INTR;
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} else {
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s->ti_size = dmalen;
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s->ti_rptr = 0;
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s->ti_wptr = 0;
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s->rregs[7] = dmalen;
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}
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pic_set_irq(s->irq, 1);
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}
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static void esp_reset(void *opaque)
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{
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ESPState *s = opaque;
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memset(s->rregs, 0, ESP_MAXREG);
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s->rregs[0x0e] = 0x4; // Indicate fas100a
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memset(s->espdmaregs, 0, ESPDMA_REGS * 4);
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}
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static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
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{
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ESPState *s = opaque;
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uint32_t saddr;
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saddr = (addr & ESP_MAXREG) >> 2;
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DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]);
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switch (saddr) {
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case 2:
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// FIFO
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if (s->ti_size > 0) {
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s->ti_size--;
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s->rregs[saddr] = s->ti_buf[s->ti_rptr++];
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pic_set_irq(s->irq, 1);
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}
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if (s->ti_size == 0) {
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s->ti_rptr = 0;
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s->ti_wptr = 0;
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}
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break;
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case 5:
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// interrupt
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// Clear status bits except TC
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s->rregs[4] &= STAT_TC;
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pic_set_irq(s->irq, 0);
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s->espdmaregs[0] &= ~DMA_INTR;
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break;
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default:
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break;
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}
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return s->rregs[saddr];
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}
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static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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ESPState *s = opaque;
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uint32_t saddr;
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saddr = (addr & ESP_MAXREG) >> 2;
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DPRINTF("write reg[%d]: 0x%2.2x -> 0x%2.2x\n", saddr, s->wregs[saddr], val);
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switch (saddr) {
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case 0:
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case 1:
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s->rregs[saddr] = val;
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break;
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case 2:
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// FIFO
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s->ti_size++;
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s->ti_buf[s->ti_wptr++] = val & 0xff;
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break;
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case 3:
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s->rregs[saddr] = val;
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// Command
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if (val & 0x80) {
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s->dma = 1;
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} else {
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s->dma = 0;
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}
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switch(val & 0x7f) {
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case 0:
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DPRINTF("NOP (%2.2x)\n", val);
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break;
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case 1:
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DPRINTF("Flush FIFO (%2.2x)\n", val);
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//s->ti_size = 0;
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s->rregs[5] = INTR_FC;
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s->rregs[6] = 0;
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break;
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case 2:
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DPRINTF("Chip reset (%2.2x)\n", val);
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esp_reset(s);
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break;
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case 3:
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DPRINTF("Bus reset (%2.2x)\n", val);
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s->rregs[5] = INTR_RST;
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if (!(s->wregs[8] & 0x40)) {
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s->espdmaregs[0] |= DMA_INTR;
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pic_set_irq(s->irq, 1);
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}
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break;
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case 0x10:
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handle_ti(s);
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break;
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case 0x11:
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DPRINTF("Initiator Command Complete Sequence (%2.2x)\n", val);
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dma_write(s, okbuf, 2);
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break;
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case 0x12:
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DPRINTF("Message Accepted (%2.2x)\n", val);
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dma_write(s, okbuf, 2);
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s->rregs[5] = INTR_DC;
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s->rregs[6] = 0;
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break;
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case 0x1a:
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DPRINTF("Set ATN (%2.2x)\n", val);
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break;
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case 0x42:
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handle_satn(s);
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break;
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case 0x43:
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DPRINTF("Set ATN & stop (%2.2x)\n", val);
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handle_satn(s);
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break;
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default:
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DPRINTF("Unhandled ESP command (%2.2x)\n", val);
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break;
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}
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break;
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case 4 ... 7:
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break;
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case 8:
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s->rregs[saddr] = val;
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break;
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case 9 ... 10:
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break;
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case 11:
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s->rregs[saddr] = val & 0x15;
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break;
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case 12 ... 15:
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s->rregs[saddr] = val;
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break;
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default:
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break;
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}
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s->wregs[saddr] = val;
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}
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static CPUReadMemoryFunc *esp_mem_read[3] = {
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esp_mem_readb,
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esp_mem_readb,
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esp_mem_readb,
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};
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static CPUWriteMemoryFunc *esp_mem_write[3] = {
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esp_mem_writeb,
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esp_mem_writeb,
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esp_mem_writeb,
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};
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static uint32_t espdma_mem_readl(void *opaque, target_phys_addr_t addr)
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{
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ESPState *s = opaque;
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uint32_t saddr;
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saddr = (addr & ESPDMA_MAXADDR) >> 2;
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DPRINTF("read dmareg[%d]: 0x%8.8x\n", saddr, s->espdmaregs[saddr]);
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return s->espdmaregs[saddr];
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}
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static void espdma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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ESPState *s = opaque;
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uint32_t saddr;
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saddr = (addr & ESPDMA_MAXADDR) >> 2;
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DPRINTF("write dmareg[%d]: 0x%8.8x -> 0x%8.8x\n", saddr, s->espdmaregs[saddr], val);
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switch (saddr) {
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case 0:
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if (!(val & DMA_INTREN))
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pic_set_irq(s->irq, 0);
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if (val & 0x80) {
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esp_reset(s);
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} else if (val & 0x40) {
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val &= ~0x40;
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} else if (val == 0)
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val = 0x40;
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val &= 0x0fffffff;
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val |= DMA_VER;
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break;
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case 1:
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s->espdmaregs[0] = DMA_LOADED;
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break;
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default:
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break;
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}
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s->espdmaregs[saddr] = val;
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}
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static CPUReadMemoryFunc *espdma_mem_read[3] = {
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espdma_mem_readl,
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espdma_mem_readl,
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espdma_mem_readl,
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};
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static CPUWriteMemoryFunc *espdma_mem_write[3] = {
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espdma_mem_writel,
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espdma_mem_writel,
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espdma_mem_writel,
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};
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static void esp_save(QEMUFile *f, void *opaque)
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{
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ESPState *s = opaque;
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unsigned int i;
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qemu_put_buffer(f, s->rregs, ESP_MAXREG);
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qemu_put_buffer(f, s->wregs, ESP_MAXREG);
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qemu_put_be32s(f, &s->irq);
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for (i = 0; i < ESPDMA_REGS; i++)
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qemu_put_be32s(f, &s->espdmaregs[i]);
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qemu_put_be32s(f, &s->ti_size);
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qemu_put_be32s(f, &s->ti_rptr);
|
|
qemu_put_be32s(f, &s->ti_wptr);
|
|
qemu_put_be32s(f, &s->ti_dir);
|
|
qemu_put_buffer(f, s->ti_buf, TI_BUFSZ);
|
|
qemu_put_be32s(f, &s->dma);
|
|
}
|
|
|
|
static int esp_load(QEMUFile *f, void *opaque, int version_id)
|
|
{
|
|
ESPState *s = opaque;
|
|
unsigned int i;
|
|
|
|
if (version_id != 1)
|
|
return -EINVAL;
|
|
|
|
qemu_get_buffer(f, s->rregs, ESP_MAXREG);
|
|
qemu_get_buffer(f, s->wregs, ESP_MAXREG);
|
|
qemu_get_be32s(f, &s->irq);
|
|
for (i = 0; i < ESPDMA_REGS; i++)
|
|
qemu_get_be32s(f, &s->espdmaregs[i]);
|
|
qemu_get_be32s(f, &s->ti_size);
|
|
qemu_get_be32s(f, &s->ti_rptr);
|
|
qemu_get_be32s(f, &s->ti_wptr);
|
|
qemu_get_be32s(f, &s->ti_dir);
|
|
qemu_get_buffer(f, s->ti_buf, TI_BUFSZ);
|
|
qemu_get_be32s(f, &s->dma);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void esp_init(BlockDriverState **bd, int irq, uint32_t espaddr, uint32_t espdaddr)
|
|
{
|
|
ESPState *s;
|
|
int esp_io_memory, espdma_io_memory;
|
|
|
|
s = qemu_mallocz(sizeof(ESPState));
|
|
if (!s)
|
|
return;
|
|
|
|
s->bd = bd;
|
|
s->irq = irq;
|
|
|
|
esp_io_memory = cpu_register_io_memory(0, esp_mem_read, esp_mem_write, s);
|
|
cpu_register_physical_memory(espaddr, ESP_MAXREG*4, esp_io_memory);
|
|
|
|
espdma_io_memory = cpu_register_io_memory(0, espdma_mem_read, espdma_mem_write, s);
|
|
cpu_register_physical_memory(espdaddr, 16, espdma_io_memory);
|
|
|
|
esp_reset(s);
|
|
|
|
register_savevm("esp", espaddr, 1, esp_save, esp_load, s);
|
|
qemu_register_reset(esp_reset, s);
|
|
}
|
|
|