c988de4119
Coverity pointed out a memory leak in riscv_sifive_e_soc_realize(),
where a pair of recently added MemoryRegion instances would not be freed
if there were errors elsewhere in the function. The fix here is to
simply not use dynamic allocation for these instances: there's always
one of each in SiFiveESoCState, so instead we just include them within
the struct.
Fixes: 30efbf330a ("SiFive RISC-V GPIO Device")
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
93 lines
2.3 KiB
C
93 lines
2.3 KiB
C
/*
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* SiFive E series machine interface
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*
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* Copyright (c) 2017 SiFive, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_SIFIVE_E_H
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#define HW_SIFIVE_E_H
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#include "hw/riscv/sifive_gpio.h"
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#define TYPE_RISCV_E_SOC "riscv.sifive.e.soc"
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#define RISCV_E_SOC(obj) \
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OBJECT_CHECK(SiFiveESoCState, (obj), TYPE_RISCV_E_SOC)
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typedef struct SiFiveESoCState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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RISCVHartArrayState cpus;
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DeviceState *plic;
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SIFIVEGPIOState gpio;
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MemoryRegion xip_mem;
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MemoryRegion mask_rom;
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} SiFiveESoCState;
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typedef struct SiFiveEState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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SiFiveESoCState soc;
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} SiFiveEState;
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enum {
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SIFIVE_E_DEBUG,
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SIFIVE_E_MROM,
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SIFIVE_E_OTP,
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SIFIVE_E_CLINT,
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SIFIVE_E_PLIC,
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SIFIVE_E_AON,
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SIFIVE_E_PRCI,
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SIFIVE_E_OTP_CTRL,
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SIFIVE_E_GPIO0,
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SIFIVE_E_UART0,
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SIFIVE_E_QSPI0,
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SIFIVE_E_PWM0,
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SIFIVE_E_UART1,
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SIFIVE_E_QSPI1,
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SIFIVE_E_PWM1,
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SIFIVE_E_QSPI2,
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SIFIVE_E_PWM2,
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SIFIVE_E_XIP,
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SIFIVE_E_DTIM
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};
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enum {
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SIFIVE_E_UART0_IRQ = 3,
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SIFIVE_E_UART1_IRQ = 4,
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SIFIVE_E_GPIO0_IRQ0 = 8
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};
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#define SIFIVE_E_PLIC_HART_CONFIG "M"
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#define SIFIVE_E_PLIC_NUM_SOURCES 127
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#define SIFIVE_E_PLIC_NUM_PRIORITIES 7
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#define SIFIVE_E_PLIC_PRIORITY_BASE 0x04
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#define SIFIVE_E_PLIC_PENDING_BASE 0x1000
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#define SIFIVE_E_PLIC_ENABLE_BASE 0x2000
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#define SIFIVE_E_PLIC_ENABLE_STRIDE 0x80
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#define SIFIVE_E_PLIC_CONTEXT_BASE 0x200000
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#define SIFIVE_E_PLIC_CONTEXT_STRIDE 0x1000
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#if defined(TARGET_RISCV32)
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#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E31
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#elif defined(TARGET_RISCV64)
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#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51
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#endif
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#endif
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