5258c2a69c
Emulate read errors in the DMA Checksum Register for high frequencies and optimistic settings of the Read Timing Compensation Register. This will help in tuning the SPI timing calibration algorithm. Errors are only injected when the property "inject_failure" is set to true as suggested by Philippe. The values below are those to expect from the first flash device of the FMC controller of a palmetto-bmc machine. Cc: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-id: 20190904070506.1052-8-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
118 lines
3.1 KiB
C
118 lines
3.1 KiB
C
/*
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* ASPEED AST2400 SMC Controller (SPI Flash Only)
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*
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* Copyright (C) 2016 IBM Corp.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef ASPEED_SMC_H
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#define ASPEED_SMC_H
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#include "hw/ssi/ssi.h"
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#include "hw/sysbus.h"
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typedef struct AspeedSegments {
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hwaddr addr;
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uint32_t size;
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} AspeedSegments;
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struct AspeedSMCState;
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typedef struct AspeedSMCController {
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const char *name;
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uint8_t r_conf;
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uint8_t r_ce_ctrl;
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uint8_t r_ctrl0;
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uint8_t r_timings;
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uint8_t conf_enable_w0;
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uint8_t max_slaves;
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const AspeedSegments *segments;
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hwaddr flash_window_base;
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uint32_t flash_window_size;
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bool has_dma;
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hwaddr dma_flash_mask;
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hwaddr dma_dram_mask;
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uint32_t nregs;
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} AspeedSMCController;
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typedef struct AspeedSMCFlash {
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struct AspeedSMCState *controller;
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uint8_t id;
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uint32_t size;
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MemoryRegion mmio;
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DeviceState *flash;
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} AspeedSMCFlash;
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#define TYPE_ASPEED_SMC "aspeed.smc"
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#define ASPEED_SMC(obj) OBJECT_CHECK(AspeedSMCState, (obj), TYPE_ASPEED_SMC)
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#define ASPEED_SMC_CLASS(klass) \
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OBJECT_CLASS_CHECK(AspeedSMCClass, (klass), TYPE_ASPEED_SMC)
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#define ASPEED_SMC_GET_CLASS(obj) \
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OBJECT_GET_CLASS(AspeedSMCClass, (obj), TYPE_ASPEED_SMC)
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typedef struct AspeedSMCClass {
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SysBusDevice parent_obj;
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const AspeedSMCController *ctrl;
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} AspeedSMCClass;
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#define ASPEED_SMC_R_MAX (0x100 / 4)
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typedef struct AspeedSMCState {
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SysBusDevice parent_obj;
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const AspeedSMCController *ctrl;
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MemoryRegion mmio;
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MemoryRegion mmio_flash;
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qemu_irq irq;
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int irqline;
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uint32_t num_cs;
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qemu_irq *cs_lines;
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bool inject_failure;
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SSIBus *spi;
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uint32_t regs[ASPEED_SMC_R_MAX];
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/* depends on the controller type */
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uint8_t r_conf;
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uint8_t r_ce_ctrl;
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uint8_t r_ctrl0;
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uint8_t r_timings;
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uint8_t conf_enable_w0;
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/* for DMA support */
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uint64_t sdram_base;
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AddressSpace flash_as;
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MemoryRegion *dram_mr;
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AddressSpace dram_as;
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AspeedSMCFlash *flashes;
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uint8_t snoop_index;
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uint8_t snoop_dummies;
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} AspeedSMCState;
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#endif /* ASPEED_SMC_H */
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