Max Chou 9d92f56d4a disas/riscv: Add support for vector crypto extensions ...

This patch adds following v1.0.0 ratified vector crypto extensions
support to the RISC-V disassembler.
- Zvbb
- Zvbc
- Zvkb
- Zvkg
- Zvkned
- Zvknha
- Zvknhb
- Zvksed
- Zvksh

Signed-off-by: Max Chou <max.chou@sifive.com>
Message-ID: <20231026151828.754279-14-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

2023-11-07 11:06:02 +10:00

..

alpha.c

…

capstone.c

disas: use result of ->read_memory_func

2022-10-06 11:53:40 +01:00

cris.c

…

disas-internal.h

disas: Move softmmu specific code to separate file

2023-05-11 09:49:55 +01:00

disas-mon.c

disas: Move softmmu specific code to separate file

2023-05-11 09:49:55 +01:00

disas.c

disas: Move disas.c into the target-independent source set

2023-05-11 09:51:07 +01:00

hexagon.c

Hexagon (disas/hexagon.c) fix memory leak for early exit cases

2021-08-12 09:06:05 -05:00

hppa.c

…

m68k.c

disas/m68k: clean up local variable shadowing

2023-09-29 10:07:21 +02:00

meson.build

disas/riscv: Add support for XThead* instructions

2023-07-10 22:29:14 +10:00

microblaze.c

…

mips.c

disas/mips: Fix branch displacement for BEQZC and BNEZC

2022-10-31 11:32:07 +01:00

nanomips.c

disas/nanomips: Tidy read for 48-bit opcodes

2022-11-08 01:04:25 +01:00

nios2.c

disas/nios2: Simplify endianess conversion

2021-10-22 18:07:30 +02:00

riscv-xthead.c

disas/riscv: Add support for XThead* instructions

2023-07-10 22:29:14 +10:00

riscv-xthead.h

disas/riscv: Add support for XThead* instructions

2023-07-10 22:29:14 +10:00

riscv-xventana.c

disas/riscv: Add support for XVentanaCondOps

2023-07-10 22:29:14 +10:00

riscv-xventana.h

disas/riscv: Add support for XVentanaCondOps

2023-07-10 22:29:14 +10:00

riscv.c

disas/riscv: Add support for vector crypto extensions

2023-11-07 11:06:02 +10:00

riscv.h

disas/riscv: Add rv_codec_vror_vi for vror.vi

2023-11-07 11:06:02 +10:00

sh4.c

…

sparc.c

…

xtensa.c

…