Lijun Pan 9d69cfa2fa target/ppc: add byte-reverse br[dwh] instructions ...

POWER ISA 3.1 introduces following byte-reverse instructions:
brd: Byte-Reverse Doubleword X-form
brw: Byte-Reverse Word X-form
brh: Byte-Reverse Halfword X-form

Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
Message-Id: <20200701234344.91843-4-ljp@linux.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>

2020-08-12 13:16:27 +10:00

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alpha

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arm

target/arm: Fix Rt/Rt2 in ESR_ELx for copro traps from AArch32 to 64

2020-08-05 17:31:51 +01:00

avr

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cris

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hppa

target/hppa: Free some temps in do_sub

2020-07-24 14:28:33 -07:00

i386

target/i386: floatx80: avoid compound literals in static initializers

2020-07-27 09:40:16 +01:00

lm32

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m68k

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microblaze

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mips

target/mips: Fix ADD.S FPU instruction

2020-07-14 21:49:33 +02:00

moxie

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nios2

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openrisc

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ppc

target/ppc: add byte-reverse br[dwh] instructions

2020-08-12 13:16:27 +10:00

riscv

target/riscv/vector_helper: Fix build on 32-bit big endian hosts

2020-08-05 10:43:45 +02:00

rx

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s390x

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sh4

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sparc

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tilegx

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tricore

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unicore32

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xtensa

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