qemu/linux-user/openrisc
Stafford Horne d89e71e873 target/openrisc: implement shadow registers
Shadow registers are part of the openrisc spec along with sr[cid], as
part of the fast context switching feature.  When exceptions occur,
instead of having to save registers to the stack if enabled the CID will
increment and a new set of registers will be available.

This patch only implements shadow registers which can be used as extra
scratch registers via the mfspr and mtspr if required.  This is
implemented in a way where it would be easy to add on the fast context
switching, currently cid is hardcoded to 0.

This is need for openrisc linux smp kernels to boot correctly.

Signed-off-by: Stafford Horne <shorne@gmail.com>
2017-05-04 09:39:01 +09:00
..
syscall_nr.h linux-user: fix TARGET_NR_select 2016-09-22 07:24:21 +03:00
target_cpu.h target/openrisc: implement shadow registers 2017-05-04 09:39:01 +09:00
target_signal.h target/openrisc: implement shadow registers 2017-05-04 09:39:01 +09:00
target_structs.h linux-user: Clean up target_structs.h header guards 2016-07-12 16:19:16 +02:00
target_syscall.h linux-user: Add MMAP_SHIFT for openrisc 2017-02-14 08:14:58 +11:00
termbits.h target-or32: Add linux syscall, signal and termbits 2012-07-27 21:13:05 +00:00