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9d316c75ab
qemu/target/avr
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Michael Rolnik 9d316c75ab target/avr: Add instruction translation - Branch Instructions 
This includes:
    - RJMP, IJMP, EIJMP, JMP
    - RCALL, ICALL, EICALL, CALL
    - RET, RETI
    - CPSE, CP, CPC, CPI
    - SBRC, SBRS, SBIC, SBIS
    - BRBC, BRBS

Signed-off-by: Michael Rolnik <mrolnik@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
Signed-off-by: Thomas Huth <huth@tuxfamily.org>
Message-Id: <20200705140315.260514-13-huth@tuxfamily.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-07-11 11:02:05 +02:00
..
cpu-param.h
cpu-qom.h
cpu.c target/avr: Add definitions of AVR core types 2020-07-10 17:58:32 +02:00
cpu.h target/avr: Introduce enumeration AVRFeature 2020-07-10 17:58:32 +02:00
gdbstub.c target/avr: CPU class: Add GDB support 2020-07-10 17:58:32 +02:00
helper.c target/avr: Add instruction helpers 2020-07-11 11:02:05 +02:00
helper.h target/avr: Add instruction helpers 2020-07-11 11:02:05 +02:00
insn.decode target/avr: Add instruction translation - Branch Instructions 2020-07-11 11:02:05 +02:00
machine.c target/avr: CPU class: Add migration support 2020-07-10 17:58:32 +02:00
translate.c target/avr: Add instruction translation - Branch Instructions 2020-07-11 11:02:05 +02:00