41f2b94ee0
The same rework did in 'priv_spec' is done for 'vext_spec'. This time is simpler, since we only accept one value ("v1.0") and we'll always have env->vext_ver set to VEXT_VERSION_1_00_0, thus we don't need helpers to convert string to 'vext_ver' back and forth like we needed for 'priv_spec'. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Tested-by: Vladimir Isaev <vladimir.isaev@syntacore.com> Message-ID: <20240105230546.265053-8-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
818 lines
24 KiB
C
818 lines
24 KiB
C
/*
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* QEMU RISC-V CPU
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*
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* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
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* Copyright (c) 2017-2018 SiFive, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef RISCV_CPU_H
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#define RISCV_CPU_H
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#include "hw/core/cpu.h"
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#include "hw/registerfields.h"
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#include "hw/qdev-properties.h"
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#include "exec/cpu-defs.h"
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#include "qemu/cpu-float.h"
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#include "qom/object.h"
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#include "qemu/int128.h"
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#include "cpu_bits.h"
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#include "cpu_cfg.h"
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#include "qapi/qapi-types-common.h"
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#include "cpu-qom.h"
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typedef struct CPUArchState CPURISCVState;
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#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
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#if defined(TARGET_RISCV32)
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# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32
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#elif defined(TARGET_RISCV64)
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# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64
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#endif
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#define TCG_GUEST_DEFAULT_MO 0
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/*
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* RISC-V-specific extra insn start words:
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* 1: Original instruction opcode
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*/
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#define TARGET_INSN_START_EXTRA_WORDS 1
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#define RV(x) ((target_ulong)1 << (x - 'A'))
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/*
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* Update misa_bits[], misa_ext_info_arr[] and misa_ext_cfgs[]
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* when adding new MISA bits here.
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*/
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#define RVI RV('I')
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#define RVE RV('E') /* E and I are mutually exclusive */
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#define RVM RV('M')
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#define RVA RV('A')
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#define RVF RV('F')
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#define RVD RV('D')
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#define RVV RV('V')
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#define RVC RV('C')
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#define RVS RV('S')
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#define RVU RV('U')
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#define RVH RV('H')
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#define RVJ RV('J')
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#define RVG RV('G')
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#define RVB RV('B')
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extern const uint32_t misa_bits[];
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const char *riscv_get_misa_ext_name(uint32_t bit);
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const char *riscv_get_misa_ext_description(uint32_t bit);
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#define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop)
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typedef struct riscv_cpu_profile {
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struct riscv_cpu_profile *parent;
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const char *name;
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uint32_t misa_ext;
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bool enabled;
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bool user_set;
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int priv_spec;
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int satp_mode;
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const int32_t ext_offsets[];
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} RISCVCPUProfile;
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#define RISCV_PROFILE_EXT_LIST_END -1
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#define RISCV_PROFILE_ATTR_UNUSED -1
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extern RISCVCPUProfile *riscv_profiles[];
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/* Privileged specification version */
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#define PRIV_VER_1_10_0_STR "v1.10.0"
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#define PRIV_VER_1_11_0_STR "v1.11.0"
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#define PRIV_VER_1_12_0_STR "v1.12.0"
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enum {
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PRIV_VERSION_1_10_0 = 0,
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PRIV_VERSION_1_11_0,
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PRIV_VERSION_1_12_0,
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PRIV_VERSION_LATEST = PRIV_VERSION_1_12_0,
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};
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#define VEXT_VERSION_1_00_0 0x00010000
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#define VEXT_VER_1_00_0_STR "v1.0"
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enum {
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TRANSLATE_SUCCESS,
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TRANSLATE_FAIL,
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TRANSLATE_PMP_FAIL,
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TRANSLATE_G_STAGE_FAIL
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};
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/* Extension context status */
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typedef enum {
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EXT_STATUS_DISABLED = 0,
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EXT_STATUS_INITIAL,
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EXT_STATUS_CLEAN,
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EXT_STATUS_DIRTY,
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} RISCVExtStatus;
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#define MMU_USER_IDX 3
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#define MAX_RISCV_PMPS (16)
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#if !defined(CONFIG_USER_ONLY)
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#include "pmp.h"
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#include "debug.h"
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#endif
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#define RV_VLEN_MAX 1024
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#define RV_MAX_MHPMEVENTS 32
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#define RV_MAX_MHPMCOUNTERS 32
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FIELD(VTYPE, VLMUL, 0, 3)
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FIELD(VTYPE, VSEW, 3, 3)
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FIELD(VTYPE, VTA, 6, 1)
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FIELD(VTYPE, VMA, 7, 1)
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FIELD(VTYPE, VEDIV, 8, 2)
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FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11)
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typedef struct PMUCTRState {
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/* Current value of a counter */
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target_ulong mhpmcounter_val;
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/* Current value of a counter in RV32 */
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target_ulong mhpmcounterh_val;
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/* Snapshot values of counter */
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target_ulong mhpmcounter_prev;
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/* Snapshort value of a counter in RV32 */
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target_ulong mhpmcounterh_prev;
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bool started;
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/* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigger */
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target_ulong irq_overflow_left;
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} PMUCTRState;
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struct CPUArchState {
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target_ulong gpr[32];
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target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */
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/* vector coprocessor state. */
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uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16);
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target_ulong vxrm;
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target_ulong vxsat;
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target_ulong vl;
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target_ulong vstart;
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target_ulong vtype;
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bool vill;
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target_ulong pc;
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target_ulong load_res;
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target_ulong load_val;
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/* Floating-Point state */
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uint64_t fpr[32]; /* assume both F and D extensions */
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target_ulong frm;
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float_status fp_status;
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target_ulong badaddr;
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target_ulong bins;
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target_ulong guest_phys_fault_addr;
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target_ulong priv_ver;
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target_ulong vext_ver;
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/* RISCVMXL, but uint32_t for vmstate migration */
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uint32_t misa_mxl; /* current mxl */
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uint32_t misa_mxl_max; /* max mxl for this cpu */
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uint32_t misa_ext; /* current extensions */
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uint32_t misa_ext_mask; /* max ext for this cpu */
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uint32_t xl; /* current xlen */
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/* 128-bit helpers upper part return value */
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target_ulong retxh;
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target_ulong jvt;
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#ifdef CONFIG_USER_ONLY
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uint32_t elf_flags;
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#endif
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#ifndef CONFIG_USER_ONLY
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target_ulong priv;
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/* This contains QEMU specific information about the virt state. */
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bool virt_enabled;
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target_ulong geilen;
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uint64_t resetvec;
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target_ulong mhartid;
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/*
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* For RV32 this is 32-bit mstatus and 32-bit mstatush.
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* For RV64 this is a 64-bit mstatus.
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*/
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uint64_t mstatus;
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uint64_t mip;
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/*
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* MIP contains the software writable version of SEIP ORed with the
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* external interrupt value. The MIP register is always up-to-date.
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* To keep track of the current source, we also save booleans of the values
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* here.
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*/
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bool external_seip;
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bool software_seip;
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uint64_t miclaim;
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uint64_t mie;
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uint64_t mideleg;
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/*
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* When mideleg[i]=0 and mvien[i]=1, sie[i] is no more
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* alias of mie[i] and needs to be maintained separately.
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*/
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uint64_t sie;
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/*
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* When hideleg[i]=0 and hvien[i]=1, vsie[i] is no more
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* alias of sie[i] (mie[i]) and needs to be maintained separately.
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*/
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uint64_t vsie;
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target_ulong satp; /* since: priv-1.10.0 */
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target_ulong stval;
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target_ulong medeleg;
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target_ulong stvec;
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target_ulong sepc;
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target_ulong scause;
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target_ulong mtvec;
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target_ulong mepc;
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target_ulong mcause;
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target_ulong mtval; /* since: priv-1.10.0 */
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/* Machine and Supervisor interrupt priorities */
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uint8_t miprio[64];
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uint8_t siprio[64];
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/* AIA CSRs */
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target_ulong miselect;
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target_ulong siselect;
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uint64_t mvien;
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uint64_t mvip;
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/* Hypervisor CSRs */
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target_ulong hstatus;
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target_ulong hedeleg;
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uint64_t hideleg;
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target_ulong hcounteren;
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target_ulong htval;
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target_ulong htinst;
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target_ulong hgatp;
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target_ulong hgeie;
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target_ulong hgeip;
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uint64_t htimedelta;
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uint64_t hvien;
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/*
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* Bits VSSIP, VSTIP and VSEIP in hvip are maintained in mip. Other bits
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* from 0:12 are reserved. Bits 13:63 are not aliased and must be separately
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* maintain in hvip.
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*/
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uint64_t hvip;
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/* Hypervisor controlled virtual interrupt priorities */
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target_ulong hvictl;
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uint8_t hviprio[64];
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/* Upper 64-bits of 128-bit CSRs */
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uint64_t mscratchh;
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uint64_t sscratchh;
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/* Virtual CSRs */
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/*
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* For RV32 this is 32-bit vsstatus and 32-bit vsstatush.
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* For RV64 this is a 64-bit vsstatus.
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*/
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uint64_t vsstatus;
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target_ulong vstvec;
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target_ulong vsscratch;
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target_ulong vsepc;
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target_ulong vscause;
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target_ulong vstval;
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target_ulong vsatp;
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/* AIA VS-mode CSRs */
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target_ulong vsiselect;
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target_ulong mtval2;
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target_ulong mtinst;
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/* HS Backup CSRs */
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target_ulong stvec_hs;
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target_ulong sscratch_hs;
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target_ulong sepc_hs;
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target_ulong scause_hs;
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target_ulong stval_hs;
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target_ulong satp_hs;
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uint64_t mstatus_hs;
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/*
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* Signals whether the current exception occurred with two-stage address
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* translation active.
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*/
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bool two_stage_lookup;
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/*
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* Signals whether the current exception occurred while doing two-stage
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* address translation for the VS-stage page table walk.
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*/
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bool two_stage_indirect_lookup;
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target_ulong scounteren;
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target_ulong mcounteren;
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target_ulong mcountinhibit;
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/* PMU counter state */
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PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS];
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/* PMU event selector configured values. First three are unused */
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target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS];
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/* PMU event selector configured values for RV32 */
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target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS];
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target_ulong sscratch;
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target_ulong mscratch;
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/* Sstc CSRs */
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uint64_t stimecmp;
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uint64_t vstimecmp;
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/* physical memory protection */
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pmp_table_t pmp_state;
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target_ulong mseccfg;
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/* trigger module */
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target_ulong trigger_cur;
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target_ulong tdata1[RV_MAX_TRIGGERS];
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target_ulong tdata2[RV_MAX_TRIGGERS];
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target_ulong tdata3[RV_MAX_TRIGGERS];
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struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS];
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struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS];
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QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS];
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int64_t last_icount;
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bool itrigger_enabled;
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/* machine specific rdtime callback */
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uint64_t (*rdtime_fn)(void *);
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void *rdtime_fn_arg;
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/* machine specific AIA ireg read-modify-write callback */
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#define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \
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((((__xlen) & 0xff) << 24) | \
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(((__vgein) & 0x3f) << 20) | \
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(((__virt) & 0x1) << 18) | \
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(((__priv) & 0x3) << 16) | \
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(__isel & 0xffff))
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#define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff)
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#define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3)
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#define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1)
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#define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f)
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#define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff)
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int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg,
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target_ulong *val, target_ulong new_val, target_ulong write_mask);
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void *aia_ireg_rmw_fn_arg[4];
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/* True if in debugger mode. */
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bool debugger;
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/*
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* CSRs for PointerMasking extension
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*/
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target_ulong mmte;
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target_ulong mpmmask;
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target_ulong mpmbase;
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target_ulong spmmask;
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target_ulong spmbase;
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target_ulong upmmask;
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target_ulong upmbase;
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/* CSRs for execution environment configuration */
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uint64_t menvcfg;
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uint64_t mstateen[SMSTATEEN_MAX_COUNT];
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uint64_t hstateen[SMSTATEEN_MAX_COUNT];
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uint64_t sstateen[SMSTATEEN_MAX_COUNT];
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target_ulong senvcfg;
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uint64_t henvcfg;
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#endif
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target_ulong cur_pmmask;
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target_ulong cur_pmbase;
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/* Fields from here on are preserved across CPU reset. */
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QEMUTimer *stimer; /* Internal timer for S-mode interrupt */
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QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */
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bool vstime_irq;
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hwaddr kernel_addr;
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hwaddr fdt_addr;
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#ifdef CONFIG_KVM
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/* kvm timer */
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bool kvm_timer_dirty;
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uint64_t kvm_timer_time;
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uint64_t kvm_timer_compare;
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uint64_t kvm_timer_state;
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uint64_t kvm_timer_frequency;
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#endif /* CONFIG_KVM */
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};
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/*
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* RISCVCPU:
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* @env: #CPURISCVState
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*
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* A RISCV CPU.
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*/
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struct ArchCPU {
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CPUState parent_obj;
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CPURISCVState env;
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char *dyn_csr_xml;
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char *dyn_vreg_xml;
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/* Configuration Settings */
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RISCVCPUConfig cfg;
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QEMUTimer *pmu_timer;
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/* A bitmask of Available programmable counters */
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uint32_t pmu_avail_ctrs;
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/* Mapping of events to counters */
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GHashTable *pmu_event_ctr_map;
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};
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/**
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* RISCVCPUClass:
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* @parent_realize: The parent class' realize handler.
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* @parent_phases: The parent class' reset phase handlers.
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*
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* A RISCV CPU model.
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*/
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struct RISCVCPUClass {
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CPUClass parent_class;
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DeviceRealize parent_realize;
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ResettablePhases parent_phases;
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};
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static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
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{
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return (env->misa_ext & ext) != 0;
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}
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#include "cpu_user.h"
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extern const char * const riscv_int_regnames[];
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extern const char * const riscv_int_regnamesh[];
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extern const char * const riscv_fpr_regnames[];
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const char *riscv_cpu_get_trap_name(target_ulong cause, bool async);
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void riscv_cpu_do_interrupt(CPUState *cpu);
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int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
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int cpuid, DumpState *s);
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int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
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int cpuid, DumpState *s);
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int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
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int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero);
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uint8_t riscv_cpu_default_priority(int irq);
|
|
uint64_t riscv_cpu_all_pending(CPURISCVState *env);
|
|
int riscv_cpu_mirq_pending(CPURISCVState *env);
|
|
int riscv_cpu_sirq_pending(CPURISCVState *env);
|
|
int riscv_cpu_vsirq_pending(CPURISCVState *env);
|
|
bool riscv_cpu_fp_enabled(CPURISCVState *env);
|
|
target_ulong riscv_cpu_get_geilen(CPURISCVState *env);
|
|
void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen);
|
|
bool riscv_cpu_vector_enabled(CPURISCVState *env);
|
|
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
|
|
int riscv_env_mmu_index(CPURISCVState *env, bool ifetch);
|
|
G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
|
|
MMUAccessType access_type,
|
|
int mmu_idx, uintptr_t retaddr);
|
|
bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
|
|
MMUAccessType access_type, int mmu_idx,
|
|
bool probe, uintptr_t retaddr);
|
|
char *riscv_isa_string(RISCVCPU *cpu);
|
|
|
|
#ifndef CONFIG_USER_ONLY
|
|
void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
|
|
vaddr addr, unsigned size,
|
|
MMUAccessType access_type,
|
|
int mmu_idx, MemTxAttrs attrs,
|
|
MemTxResult response, uintptr_t retaddr);
|
|
hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
|
|
bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
|
|
void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
|
|
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts);
|
|
uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask,
|
|
uint64_t value);
|
|
void riscv_cpu_interrupt(CPURISCVState *env);
|
|
#define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
|
|
void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *),
|
|
void *arg);
|
|
void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv,
|
|
int (*rmw_fn)(void *arg,
|
|
target_ulong reg,
|
|
target_ulong *val,
|
|
target_ulong new_val,
|
|
target_ulong write_mask),
|
|
void *rmw_fn_arg);
|
|
|
|
RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit);
|
|
#endif
|
|
void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
|
|
|
|
void riscv_translate_init(void);
|
|
G_NORETURN void riscv_raise_exception(CPURISCVState *env,
|
|
uint32_t exception, uintptr_t pc);
|
|
|
|
target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
|
|
void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
|
|
|
|
#include "exec/cpu-all.h"
|
|
|
|
FIELD(TB_FLAGS, MEM_IDX, 0, 3)
|
|
FIELD(TB_FLAGS, FS, 3, 2)
|
|
/* Vector flags */
|
|
FIELD(TB_FLAGS, VS, 5, 2)
|
|
FIELD(TB_FLAGS, LMUL, 7, 3)
|
|
FIELD(TB_FLAGS, SEW, 10, 3)
|
|
FIELD(TB_FLAGS, VL_EQ_VLMAX, 13, 1)
|
|
FIELD(TB_FLAGS, VILL, 14, 1)
|
|
FIELD(TB_FLAGS, VSTART_EQ_ZERO, 15, 1)
|
|
/* The combination of MXL/SXL/UXL that applies to the current cpu mode. */
|
|
FIELD(TB_FLAGS, XL, 16, 2)
|
|
/* If PointerMasking should be applied */
|
|
FIELD(TB_FLAGS, PM_MASK_ENABLED, 18, 1)
|
|
FIELD(TB_FLAGS, PM_BASE_ENABLED, 19, 1)
|
|
FIELD(TB_FLAGS, VTA, 20, 1)
|
|
FIELD(TB_FLAGS, VMA, 21, 1)
|
|
/* Native debug itrigger */
|
|
FIELD(TB_FLAGS, ITRIGGER, 22, 1)
|
|
/* Virtual mode enabled */
|
|
FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1)
|
|
FIELD(TB_FLAGS, PRIV, 24, 2)
|
|
FIELD(TB_FLAGS, AXL, 26, 2)
|
|
|
|
#ifdef TARGET_RISCV32
|
|
#define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)
|
|
#else
|
|
static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
|
|
{
|
|
return env->misa_mxl;
|
|
}
|
|
#endif
|
|
#define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env)))
|
|
|
|
static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env)
|
|
{
|
|
return &env_archcpu(env)->cfg;
|
|
}
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
static inline int cpu_address_mode(CPURISCVState *env)
|
|
{
|
|
int mode = env->priv;
|
|
|
|
if (mode == PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) {
|
|
mode = get_field(env->mstatus, MSTATUS_MPP);
|
|
}
|
|
return mode;
|
|
}
|
|
|
|
static inline RISCVMXL cpu_get_xl(CPURISCVState *env, target_ulong mode)
|
|
{
|
|
RISCVMXL xl = env->misa_mxl;
|
|
/*
|
|
* When emulating a 32-bit-only cpu, use RV32.
|
|
* When emulating a 64-bit cpu, and MXL has been reduced to RV32,
|
|
* MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened
|
|
* back to RV64 for lower privs.
|
|
*/
|
|
if (xl != MXL_RV32) {
|
|
switch (mode) {
|
|
case PRV_M:
|
|
break;
|
|
case PRV_U:
|
|
xl = get_field(env->mstatus, MSTATUS64_UXL);
|
|
break;
|
|
default: /* PRV_S */
|
|
xl = get_field(env->mstatus, MSTATUS64_SXL);
|
|
break;
|
|
}
|
|
}
|
|
return xl;
|
|
}
|
|
#endif
|
|
|
|
#if defined(TARGET_RISCV32)
|
|
#define cpu_recompute_xl(env) ((void)(env), MXL_RV32)
|
|
#else
|
|
static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env)
|
|
{
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
return cpu_get_xl(env, env->priv);
|
|
#else
|
|
return env->misa_mxl;
|
|
#endif
|
|
}
|
|
#endif
|
|
|
|
#if defined(TARGET_RISCV32)
|
|
#define cpu_address_xl(env) ((void)(env), MXL_RV32)
|
|
#else
|
|
static inline RISCVMXL cpu_address_xl(CPURISCVState *env)
|
|
{
|
|
#ifdef CONFIG_USER_ONLY
|
|
return env->xl;
|
|
#else
|
|
int mode = cpu_address_mode(env);
|
|
|
|
return cpu_get_xl(env, mode);
|
|
#endif
|
|
}
|
|
#endif
|
|
|
|
static inline int riscv_cpu_xlen(CPURISCVState *env)
|
|
{
|
|
return 16 << env->xl;
|
|
}
|
|
|
|
#ifdef TARGET_RISCV32
|
|
#define riscv_cpu_sxl(env) ((void)(env), MXL_RV32)
|
|
#else
|
|
static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env)
|
|
{
|
|
#ifdef CONFIG_USER_ONLY
|
|
return env->misa_mxl;
|
|
#else
|
|
return get_field(env->mstatus, MSTATUS64_SXL);
|
|
#endif
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Encode LMUL to lmul as follows:
|
|
* LMUL vlmul lmul
|
|
* 1 000 0
|
|
* 2 001 1
|
|
* 4 010 2
|
|
* 8 011 3
|
|
* - 100 -
|
|
* 1/8 101 -3
|
|
* 1/4 110 -2
|
|
* 1/2 111 -1
|
|
*
|
|
* then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul)
|
|
* e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8
|
|
* => VLMAX = vlen >> (1 + 3 - (-3))
|
|
* = 256 >> 7
|
|
* = 2
|
|
*/
|
|
static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype)
|
|
{
|
|
uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW);
|
|
int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3);
|
|
return cpu->cfg.vlen >> (sew + 3 - lmul);
|
|
}
|
|
|
|
void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
|
|
uint64_t *cs_base, uint32_t *pflags);
|
|
|
|
void riscv_cpu_update_mask(CPURISCVState *env);
|
|
bool riscv_cpu_is_32bit(RISCVCPU *cpu);
|
|
|
|
RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
|
|
target_ulong *ret_value,
|
|
target_ulong new_value, target_ulong write_mask);
|
|
RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
|
|
target_ulong *ret_value,
|
|
target_ulong new_value,
|
|
target_ulong write_mask);
|
|
|
|
static inline void riscv_csr_write(CPURISCVState *env, int csrno,
|
|
target_ulong val)
|
|
{
|
|
riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS));
|
|
}
|
|
|
|
static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
|
|
{
|
|
target_ulong val = 0;
|
|
riscv_csrrw(env, csrno, &val, 0, 0);
|
|
return val;
|
|
}
|
|
|
|
typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env,
|
|
int csrno);
|
|
typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,
|
|
target_ulong *ret_value);
|
|
typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno,
|
|
target_ulong new_value);
|
|
typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
|
|
target_ulong *ret_value,
|
|
target_ulong new_value,
|
|
target_ulong write_mask);
|
|
|
|
RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
|
|
Int128 *ret_value,
|
|
Int128 new_value, Int128 write_mask);
|
|
|
|
typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno,
|
|
Int128 *ret_value);
|
|
typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno,
|
|
Int128 new_value);
|
|
|
|
typedef struct {
|
|
const char *name;
|
|
riscv_csr_predicate_fn predicate;
|
|
riscv_csr_read_fn read;
|
|
riscv_csr_write_fn write;
|
|
riscv_csr_op_fn op;
|
|
riscv_csr_read128_fn read128;
|
|
riscv_csr_write128_fn write128;
|
|
/* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */
|
|
uint32_t min_priv_ver;
|
|
} riscv_csr_operations;
|
|
|
|
/* CSR function table constants */
|
|
enum {
|
|
CSR_TABLE_SIZE = 0x1000
|
|
};
|
|
|
|
/*
|
|
* The event id are encoded based on the encoding specified in the
|
|
* SBI specification v0.3
|
|
*/
|
|
|
|
enum riscv_pmu_event_idx {
|
|
RISCV_PMU_EVENT_HW_CPU_CYCLES = 0x01,
|
|
RISCV_PMU_EVENT_HW_INSTRUCTIONS = 0x02,
|
|
RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS = 0x10019,
|
|
RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS = 0x1001B,
|
|
RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021,
|
|
};
|
|
|
|
/* used by tcg/tcg-cpu.c*/
|
|
void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en);
|
|
bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset);
|
|
void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext);
|
|
bool riscv_cpu_is_vendor(Object *cpu_obj);
|
|
|
|
typedef struct RISCVCPUMultiExtConfig {
|
|
const char *name;
|
|
uint32_t offset;
|
|
bool enabled;
|
|
} RISCVCPUMultiExtConfig;
|
|
|
|
extern const RISCVCPUMultiExtConfig riscv_cpu_extensions[];
|
|
extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[];
|
|
extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[];
|
|
extern const RISCVCPUMultiExtConfig riscv_cpu_named_features[];
|
|
extern const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[];
|
|
extern Property riscv_cpu_options[];
|
|
|
|
typedef struct isa_ext_data {
|
|
const char *name;
|
|
int min_version;
|
|
int ext_enable_offset;
|
|
} RISCVIsaExtData;
|
|
extern const RISCVIsaExtData isa_edata_arr[];
|
|
char *riscv_cpu_get_name(RISCVCPU *cpu);
|
|
|
|
void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp);
|
|
void riscv_add_satp_mode_properties(Object *obj);
|
|
bool riscv_cpu_accelerator_compatible(RISCVCPU *cpu);
|
|
|
|
/* CSR function table */
|
|
extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
|
|
|
|
extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[];
|
|
|
|
void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
|
|
void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
|
|
|
|
void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
|
|
|
|
uint8_t satp_mode_max_from_map(uint32_t map);
|
|
const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
|
|
|
|
#endif /* RISCV_CPU_H */
|