400 lines
14 KiB
C
400 lines
14 KiB
C
/*
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* PA-RISC emulation cpu definitions for qemu.
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*
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* Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HPPA_CPU_H
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#define HPPA_CPU_H
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#include "cpu-qom.h"
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#include "exec/cpu-defs.h"
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#include "qemu/cpu-float.h"
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#include "qemu/interval-tree.h"
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/* PA-RISC 1.x processors have a strong memory model. */
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/* ??? While we do not yet implement PA-RISC 2.0, those processors have
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a weak memory model, but with TLB bits that force ordering on a per-page
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basis. It's probably easier to fall back to a strong memory model. */
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#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
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#define MMU_KERNEL_IDX 7
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#define MMU_KERNEL_P_IDX 8
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#define MMU_PL1_IDX 9
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#define MMU_PL1_P_IDX 10
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#define MMU_PL2_IDX 11
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#define MMU_PL2_P_IDX 12
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#define MMU_USER_IDX 13
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#define MMU_USER_P_IDX 14
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#define MMU_PHYS_IDX 15
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#define MMU_IDX_TO_PRIV(MIDX) (((MIDX) - MMU_KERNEL_IDX) / 2)
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#define MMU_IDX_TO_P(MIDX) (((MIDX) - MMU_KERNEL_IDX) & 1)
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#define PRIV_P_TO_MMU_IDX(PRIV, P) ((PRIV) * 2 + !!(P) + MMU_KERNEL_IDX)
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#define TARGET_INSN_START_EXTRA_WORDS 1
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/* No need to flush MMU_PHYS_IDX */
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#define HPPA_MMU_FLUSH_MASK \
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(1 << MMU_KERNEL_IDX | 1 << MMU_KERNEL_P_IDX | \
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1 << MMU_PL1_IDX | 1 << MMU_PL1_P_IDX | \
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1 << MMU_PL2_IDX | 1 << MMU_PL2_P_IDX | \
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1 << MMU_USER_IDX | 1 << MMU_USER_P_IDX)
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/* Indicies to flush for access_id changes. */
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#define HPPA_MMU_FLUSH_P_MASK \
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(1 << MMU_KERNEL_P_IDX | 1 << MMU_PL1_P_IDX | \
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1 << MMU_PL2_P_IDX | 1 << MMU_USER_P_IDX)
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/* Hardware exceptions, interrupts, faults, and traps. */
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#define EXCP_HPMC 1 /* high priority machine check */
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#define EXCP_POWER_FAIL 2
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#define EXCP_RC 3 /* recovery counter */
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#define EXCP_EXT_INTERRUPT 4 /* external interrupt */
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#define EXCP_LPMC 5 /* low priority machine check */
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#define EXCP_ITLB_MISS 6 /* itlb miss / instruction page fault */
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#define EXCP_IMP 7 /* instruction memory protection trap */
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#define EXCP_ILL 8 /* illegal instruction trap */
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#define EXCP_BREAK 9 /* break instruction */
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#define EXCP_PRIV_OPR 10 /* privileged operation trap */
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#define EXCP_PRIV_REG 11 /* privileged register trap */
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#define EXCP_OVERFLOW 12 /* signed overflow trap */
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#define EXCP_COND 13 /* trap-on-condition */
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#define EXCP_ASSIST 14 /* assist exception trap */
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#define EXCP_DTLB_MISS 15 /* dtlb miss / data page fault */
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#define EXCP_NA_ITLB_MISS 16 /* non-access itlb miss */
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#define EXCP_NA_DTLB_MISS 17 /* non-access dtlb miss */
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#define EXCP_DMP 18 /* data memory protection trap */
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#define EXCP_DMB 19 /* data memory break trap */
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#define EXCP_TLB_DIRTY 20 /* tlb dirty bit trap */
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#define EXCP_PAGE_REF 21 /* page reference trap */
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#define EXCP_ASSIST_EMU 22 /* assist emulation trap */
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#define EXCP_HPT 23 /* high-privilege transfer trap */
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#define EXCP_LPT 24 /* low-privilege transfer trap */
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#define EXCP_TB 25 /* taken branch trap */
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#define EXCP_DMAR 26 /* data memory access rights trap */
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#define EXCP_DMPI 27 /* data memory protection id trap */
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#define EXCP_UNALIGN 28 /* unaligned data reference trap */
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#define EXCP_PER_INTERRUPT 29 /* performance monitor interrupt */
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/* Exceptions for linux-user emulation. */
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#define EXCP_SYSCALL 30
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#define EXCP_SYSCALL_LWS 31
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/* Emulated hardware TOC button */
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#define EXCP_TOC 32 /* TOC = Transfer of control (NMI) */
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#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 /* TOC */
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/* Taken from Linux kernel: arch/parisc/include/asm/psw.h */
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#define PSW_I 0x00000001
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#define PSW_D 0x00000002
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#define PSW_P 0x00000004
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#define PSW_Q 0x00000008
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#define PSW_R 0x00000010
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#define PSW_F 0x00000020
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#define PSW_G 0x00000040 /* PA1.x only */
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#define PSW_O 0x00000080 /* PA2.0 only */
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#define PSW_CB 0x0000ff00
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#define PSW_M 0x00010000
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#define PSW_V 0x00020000
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#define PSW_C 0x00040000
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#define PSW_B 0x00080000
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#define PSW_X 0x00100000
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#define PSW_N 0x00200000
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#define PSW_L 0x00400000
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#define PSW_H 0x00800000
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#define PSW_T 0x01000000
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#define PSW_S 0x02000000
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#define PSW_E 0x04000000
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#ifdef TARGET_HPPA64
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#define PSW_W 0x08000000 /* PA2.0 only */
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#else
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#define PSW_W 0
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#endif
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#define PSW_Z 0x40000000 /* PA1.x only */
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#define PSW_Y 0x80000000 /* PA1.x only */
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#define PSW_SM (PSW_W | PSW_E | PSW_O | PSW_G | PSW_F \
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| PSW_R | PSW_Q | PSW_P | PSW_D | PSW_I)
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/* ssm/rsm instructions number PSW_W and PSW_E differently */
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#define PSW_SM_I PSW_I /* Enable External Interrupts */
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#define PSW_SM_D PSW_D
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#define PSW_SM_P PSW_P
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#define PSW_SM_Q PSW_Q /* Enable Interrupt State Collection */
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#define PSW_SM_R PSW_R /* Enable Recover Counter Trap */
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#ifdef TARGET_HPPA64
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#define PSW_SM_E 0x100
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#define PSW_SM_W 0x200 /* PA2.0 only : Enable Wide Mode */
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#else
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#define PSW_SM_E 0
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#define PSW_SM_W 0
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#endif
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#define CR_RC 0
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#define CR_PID1 8
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#define CR_PID2 9
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#define CR_PID3 12
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#define CR_PID4 13
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#define CR_SCRCCR 10
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#define CR_SAR 11
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#define CR_IVA 14
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#define CR_EIEM 15
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#define CR_IT 16
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#define CR_IIASQ 17
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#define CR_IIAOQ 18
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#define CR_IIR 19
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#define CR_ISR 20
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#define CR_IOR 21
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#define CR_IPSW 22
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#define CR_EIRR 23
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#if TARGET_REGISTER_BITS == 32
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typedef uint32_t target_ureg;
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typedef int32_t target_sreg;
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#define TREG_FMT_lx "%08"PRIx32
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#define TREG_FMT_ld "%"PRId32
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#else
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typedef uint64_t target_ureg;
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typedef int64_t target_sreg;
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#define TREG_FMT_lx "%016"PRIx64
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#define TREG_FMT_ld "%"PRId64
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#endif
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typedef struct HPPATLBEntry {
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union {
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IntervalTreeNode itree;
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struct HPPATLBEntry *unused_next;
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};
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target_ureg pa;
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unsigned entry_valid : 1;
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unsigned u : 1;
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unsigned t : 1;
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unsigned d : 1;
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unsigned b : 1;
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unsigned ar_type : 3;
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unsigned ar_pl1 : 2;
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unsigned ar_pl2 : 2;
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unsigned access_id : 16;
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} HPPATLBEntry;
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typedef struct CPUArchState {
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target_ureg iaoq_f; /* front */
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target_ureg iaoq_b; /* back, aka next instruction */
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target_ureg gr[32];
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uint64_t fr[32];
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uint64_t sr[8]; /* stored shifted into place for gva */
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target_ureg psw; /* All psw bits except the following: */
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target_ureg psw_n; /* boolean */
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target_sreg psw_v; /* in most significant bit */
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/* Splitting the carry-borrow field into the MSB and "the rest", allows
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* for "the rest" to be deleted when it is unused, but the MSB is in use.
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* In addition, it's easier to compute carry-in for bit B+1 than it is to
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* compute carry-out for bit B (3 vs 4 insns for addition, assuming the
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* host has the appropriate add-with-carry insn to compute the msb).
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* Therefore the carry bits are stored as: cb_msb : cb & 0x11111110.
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*/
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target_ureg psw_cb; /* in least significant bit of next nibble */
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target_ureg psw_cb_msb; /* boolean */
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uint64_t iasq_f;
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uint64_t iasq_b;
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uint32_t fr0_shadow; /* flags, c, ca/cq, rm, d, enables */
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float_status fp_status;
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target_ureg cr[32]; /* control registers */
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target_ureg cr_back[2]; /* back of cr17/cr18 */
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target_ureg shadow[7]; /* shadow registers */
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/*
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* ??? The number of entries isn't specified by the architecture.
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* BTLBs are not supported in 64-bit machines.
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*/
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#define PA10_BTLB_FIXED 16
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#define PA10_BTLB_VARIABLE 0
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#define HPPA_TLB_ENTRIES 256
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/* Index for round-robin tlb eviction. */
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uint32_t tlb_last;
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/*
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* For pa1.x, the partial initialized, still invalid tlb entry
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* which has had ITLBA performed, but not yet ITLBP.
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*/
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HPPATLBEntry *tlb_partial;
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/* Linked list of all invalid (unused) tlb entries. */
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HPPATLBEntry *tlb_unused;
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/* Root of the search tree for all valid tlb entries. */
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IntervalTreeRoot tlb_root;
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HPPATLBEntry tlb[HPPA_TLB_ENTRIES];
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} CPUHPPAState;
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/**
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* HPPACPU:
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* @env: #CPUHPPAState
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*
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* An HPPA CPU.
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*/
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struct ArchCPU {
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/*< private >*/
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CPUState parent_obj;
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/*< public >*/
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CPUHPPAState env;
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QEMUTimer *alarm_timer;
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};
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#include "exec/cpu-all.h"
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static inline bool hppa_is_pa20(CPUHPPAState *env)
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{
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return object_dynamic_cast(OBJECT(env_cpu(env)), TYPE_HPPA64_CPU) != NULL;
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}
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static inline int HPPA_BTLB_ENTRIES(CPUHPPAState *env)
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{
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return hppa_is_pa20(env) ? 0 : PA10_BTLB_FIXED + PA10_BTLB_VARIABLE;
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}
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static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch)
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{
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#ifdef CONFIG_USER_ONLY
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return MMU_USER_IDX;
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#else
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if (env->psw & (ifetch ? PSW_C : PSW_D)) {
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return PRIV_P_TO_MMU_IDX(env->iaoq_f & 3, env->psw & PSW_P);
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}
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return MMU_PHYS_IDX; /* mmu disabled */
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#endif
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}
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void hppa_translate_init(void);
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#define CPU_RESOLVING_TYPE TYPE_HPPA_CPU
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static inline target_ulong hppa_form_gva_psw(target_ureg psw, uint64_t spc,
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target_ureg off)
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{
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#ifdef CONFIG_USER_ONLY
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return off;
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#else
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off &= (psw & PSW_W ? 0x3fffffffffffffffull : 0xffffffffull);
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return spc | off;
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#endif
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}
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static inline target_ulong hppa_form_gva(CPUHPPAState *env, uint64_t spc,
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target_ureg off)
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{
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return hppa_form_gva_psw(env->psw, spc, off);
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}
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/*
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* Since PSW_{I,CB} will never need to be in tb->flags, reuse them.
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* TB_FLAG_SR_SAME indicates that SR4 through SR7 all contain the
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* same value.
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*/
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#define TB_FLAG_SR_SAME PSW_I
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#define TB_FLAG_PRIV_SHIFT 8
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#define TB_FLAG_UNALIGN 0x400
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static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc,
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uint64_t *cs_base, uint32_t *pflags)
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{
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uint32_t flags = env->psw_n * PSW_N;
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/* TB lookup assumes that PC contains the complete virtual address.
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If we leave space+offset separate, we'll get ITLB misses to an
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incomplete virtual address. This also means that we must separate
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out current cpu privilege from the low bits of IAOQ_F. */
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#ifdef CONFIG_USER_ONLY
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*pc = env->iaoq_f & -4;
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*cs_base = env->iaoq_b & -4;
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flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
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#else
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/* ??? E, T, H, L, B bits need to be here, when implemented. */
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flags |= env->psw & (PSW_W | PSW_C | PSW_D | PSW_P);
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flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT;
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*pc = (env->psw & PSW_C
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? hppa_form_gva_psw(env->psw, env->iasq_f, env->iaoq_f & -4)
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: env->iaoq_f & -4);
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*cs_base = env->iasq_f;
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/* Insert a difference between IAOQ_B and IAOQ_F within the otherwise zero
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low 32-bits of CS_BASE. This will succeed for all direct branches,
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which is the primary case we care about -- using goto_tb within a page.
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Failure is indicated by a zero difference. */
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if (env->iasq_f == env->iasq_b) {
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target_sreg diff = env->iaoq_b - env->iaoq_f;
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if (TARGET_REGISTER_BITS == 32 || diff == (int32_t)diff) {
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*cs_base |= (uint32_t)diff;
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}
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}
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if ((env->sr[4] == env->sr[5])
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& (env->sr[4] == env->sr[6])
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& (env->sr[4] == env->sr[7])) {
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flags |= TB_FLAG_SR_SAME;
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}
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#endif
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*pflags = flags;
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}
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target_ureg cpu_hppa_get_psw(CPUHPPAState *env);
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void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg);
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void cpu_hppa_loaded_fr0(CPUHPPAState *env);
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#ifdef CONFIG_USER_ONLY
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static inline void cpu_hppa_change_prot_id(CPUHPPAState *env) { }
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#else
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void cpu_hppa_change_prot_id(CPUHPPAState *env);
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#endif
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int hppa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
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int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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void hppa_cpu_dump_state(CPUState *cs, FILE *f, int);
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#ifndef CONFIG_USER_ONLY
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void hppa_ptlbe(CPUHPPAState *env);
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hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr);
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bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr);
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void hppa_cpu_do_interrupt(CPUState *cpu);
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bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req);
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int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx,
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int type, hwaddr *pphys, int *pprot,
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HPPATLBEntry **tlb_entry);
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extern const MemoryRegionOps hppa_io_eir_ops;
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extern const VMStateDescription vmstate_hppa_cpu;
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void hppa_cpu_alarm_timer(void *);
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int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr);
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#endif
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G_NORETURN void hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra);
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#endif /* HPPA_CPU_H */
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