6fe6d6c9a9
The company 'Arm' went through a rebranding some years back involving a recapitalization from 'ARM' to 'Arm'. As a result our documentation is a bit inconsistent between the two forms. It's not worth trying to update everywhere in QEMU, but it's easy enough to make docs/ consistent. Note that "ARMv8" and similar architecture names, and older CPU names like "ARM926" still retain all-caps. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> Message-id: 20200309215818.2021-6-peter.maydell@linaro.org
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4.8 KiB
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112 lines
4.8 KiB
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====================
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Translator Internals
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====================
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QEMU is a dynamic translator. When it first encounters a piece of code,
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it converts it to the host instruction set. Usually dynamic translators
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are very complicated and highly CPU dependent. QEMU uses some tricks
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which make it relatively easily portable and simple while achieving good
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performances.
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QEMU's dynamic translation backend is called TCG, for "Tiny Code
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Generator". For more information, please take a look at ``tcg/README``.
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Some notable features of QEMU's dynamic translator are:
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CPU state optimisations
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-----------------------
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The target CPUs have many internal states which change the way it
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evaluates instructions. In order to achieve a good speed, the
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translation phase considers that some state information of the virtual
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CPU cannot change in it. The state is recorded in the Translation
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Block (TB). If the state changes (e.g. privilege level), a new TB will
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be generated and the previous TB won't be used anymore until the state
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matches the state recorded in the previous TB. The same idea can be applied
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to other aspects of the CPU state. For example, on x86, if the SS,
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DS and ES segments have a zero base, then the translator does not even
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generate an addition for the segment base.
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Direct block chaining
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---------------------
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After each translated basic block is executed, QEMU uses the simulated
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Program Counter (PC) and other cpu state information (such as the CS
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segment base value) to find the next basic block.
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In order to accelerate the most common cases where the new simulated PC
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is known, QEMU can patch a basic block so that it jumps directly to the
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next one.
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The most portable code uses an indirect jump. An indirect jump makes
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it easier to make the jump target modification atomic. On some host
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architectures (such as x86 or PowerPC), the ``JUMP`` opcode is
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directly patched so that the block chaining has no overhead.
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Self-modifying code and translated code invalidation
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----------------------------------------------------
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Self-modifying code is a special challenge in x86 emulation because no
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instruction cache invalidation is signaled by the application when code
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is modified.
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User-mode emulation marks a host page as write-protected (if it is
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not already read-only) every time translated code is generated for a
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basic block. Then, if a write access is done to the page, Linux raises
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a SEGV signal. QEMU then invalidates all the translated code in the page
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and enables write accesses to the page. For system emulation, write
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protection is achieved through the software MMU.
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Correct translated code invalidation is done efficiently by maintaining
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a linked list of every translated block contained in a given page. Other
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linked lists are also maintained to undo direct block chaining.
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On RISC targets, correctly written software uses memory barriers and
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cache flushes, so some of the protection above would not be
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necessary. However, QEMU still requires that the generated code always
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matches the target instructions in memory in order to handle
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exceptions correctly.
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Exception support
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-----------------
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longjmp() is used when an exception such as division by zero is
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encountered.
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The host SIGSEGV and SIGBUS signal handlers are used to get invalid
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memory accesses. QEMU keeps a map from host program counter to
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target program counter, and looks up where the exception happened
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based on the host program counter at the exception point.
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On some targets, some bits of the virtual CPU's state are not flushed to the
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memory until the end of the translation block. This is done for internal
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emulation state that is rarely accessed directly by the program and/or changes
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very often throughout the execution of a translation block---this includes
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condition codes on x86, delay slots on SPARC, conditional execution on
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Arm, and so on. This state is stored for each target instruction, and
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looked up on exceptions.
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MMU emulation
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-------------
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For system emulation QEMU uses a software MMU. In that mode, the MMU
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virtual to physical address translation is done at every memory
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access.
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QEMU uses an address translation cache (TLB) to speed up the translation.
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In order to avoid flushing the translated code each time the MMU
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mappings change, all caches in QEMU are physically indexed. This
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means that each basic block is indexed with its physical address.
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In order to avoid invalidating the basic block chain when MMU mappings
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change, chaining is only performed when the destination of the jump
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shares a page with the basic block that is performing the jump.
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The MMU can also distinguish RAM and ROM memory areas from MMIO memory
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areas. Access is faster for RAM and ROM because the translation cache also
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hosts the offset between guest address and host memory. Accessing MMIO
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memory areas instead calls out to C code for device emulation.
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Finally, the MMU helps tracking dirty pages and pages pointed to by
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translation blocks.
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