qemu/target
Daniel Henrique Barboza 9c5180d799 target/riscv: introduce TCG AccelCPUClass
target/riscv/cpu.c needs to handle all possible accelerators (TCG and
KVM at this moment) during both init() and realize() time. This forces
us to resort to a lot of "if tcg" and "if kvm" throughout the code,
which isn't wrong, but can get cluttered over time. Splitting
acceleration specific code from cpu.c to its own file will help to
declutter the existing code and it will also make it easier to support
KVM/TCG only builds in the future.

We'll start by adding a new subdir called 'tcg' and a new file called
'tcg-cpu.c'. This file will be used to introduce a new accelerator class
for TCG acceleration in RISC-V, allowing us to center all TCG exclusive
code in its file instead of using 'cpu.c' for everything. This design is
inpired by the work Claudio Fontana did in x86 a few years ago in commit
f5cc5a5c1 ("i386: split cpu accelerators from cpu.c, using
AccelCPUClass").

To avoid moving too much code at once we'll start by adding the new file
and TCG AccelCPUClass declaration. The 'class_init' from the accel class
will init 'tcg_ops', relieving the common riscv_cpu_class_init() from
doing it.

'riscv_tcg_ops' is being exported from 'cpu.c' for now to avoid having
to deal with moving code and files around right now. We'll focus on
decoupling the realize() logic first.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-10-12 11:55:21 +10:00
..
alpha meson: Rename target_softmmu_arch -> target_system_arch 2023-10-07 19:03:07 +02:00
arm target/arm: Remove references to gdb_has_xml 2023-10-11 08:46:33 +01:00
avr meson: Rename target_softmmu_arch -> target_system_arch 2023-10-07 19:03:07 +02:00
cris meson: Rename target_softmmu_arch -> target_system_arch 2023-10-07 19:03:07 +02:00
hexagon accel/tcg: Remove cpu_set_cpustate_pointers 2023-10-04 11:03:54 -07:00
hppa meson: Rename target_softmmu_arch -> target_system_arch 2023-10-07 19:03:07 +02:00
i386 hw/core/cpu: Return static value with gdb_arch_name() 2023-10-11 08:46:33 +01:00
loongarch hw/core/cpu: Return static value with gdb_arch_name() 2023-10-11 08:46:33 +01:00
m68k meson: Rename target_softmmu_arch -> target_system_arch 2023-10-07 19:03:07 +02:00
microblaze meson: Rename target_softmmu_arch -> target_system_arch 2023-10-07 19:03:07 +02:00
mips meson: Rename target_softmmu_arch -> target_system_arch 2023-10-07 19:03:07 +02:00
nios2 meson: Rename target_softmmu_arch -> target_system_arch 2023-10-07 19:03:07 +02:00
openrisc meson: Rename target_softmmu_arch -> target_system_arch 2023-10-07 19:03:07 +02:00
ppc target/ppc: Remove references to gdb_has_xml 2023-10-11 08:46:33 +01:00
riscv target/riscv: introduce TCG AccelCPUClass 2023-10-12 11:55:21 +10:00
rx meson: Rename target_softmmu_arch -> target_system_arch 2023-10-07 19:03:07 +02:00
s390x hw/core/cpu: Return static value with gdb_arch_name() 2023-10-11 08:46:33 +01:00
sh4 target/sh4: Disable decode_gusa when plugins enabled 2023-10-11 08:46:36 +01:00
sparc meson: Rename target_softmmu_arch -> target_system_arch 2023-10-07 19:03:07 +02:00
tricore hw/core/cpu: Return static value with gdb_arch_name() 2023-10-11 08:46:33 +01:00
xtensa meson: Rename target_softmmu_arch -> target_system_arch 2023-10-07 19:03:07 +02:00
Kconfig hw/loongarch: Add support loongson3 virt machine type. 2022-06-06 18:09:03 +00:00
meson.build target/loongarch: Add target build suport 2022-06-06 18:09:03 +00:00