Palmer Dabbelt 9c0fb20c4b RISC-V: virt: This is a "sifive,test1" test finisher ... The test finisher implements the reset command, which means it's a "sifive,test1" device. This is a backwards compatible change, so it's also a "sifive,test0" device. I copied the odd idiom for adding a two-string compatible field from the ARM virt board. Fixes: 9a2551ed6f ("riscv: sifive_test: Add reset functionality") Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>		2019-11-25 12:34:52 -08:00
..
boot.c	riscv/boot: Fix possible memory leak	2019-10-28 08:46:06 -07:00
Kconfig	riscv/virt: Add the PFlash CFI01 device	2019-10-28 07:47:28 -07:00
Makefile.objs	riscv: sifive: Implement a model for SiFive FU540 OTP	2019-09-17 08:42:49 -07:00
riscv_hart.c	riscv: hart: Add a "hartid-base" property to RISC-V hart array	2019-09-17 08:42:47 -07:00
riscv_htif.c
sifive_clint.c	Include hw/qdev-properties.h less	2019-08-16 13:31:53 +02:00
sifive_e_prci.c	riscv: sifive_e: prci: Update the PRCI register block size	2019-09-17 08:42:46 -07:00
sifive_e.c	riscv: sifive_e: Drop sifive_mmio_emulate()	2019-09-17 08:42:46 -07:00
sifive_gpio.c
sifive_plic.c	riscv: plic: Remove unused interrupt functions	2019-09-17 08:42:42 -07:00
sifive_test.c	riscv: hw: Remove the unnecessary include of target/riscv/cpu.h	2019-09-17 08:42:45 -07:00
sifive_u_otp.c	riscv: sifive: Implement a model for SiFive FU540 OTP	2019-09-17 08:42:49 -07:00
sifive_u_prci.c	riscv: sifive: Implement PRCI model for FU540	2019-09-17 08:42:47 -07:00
sifive_u.c	riscv/sifive_u: Add the start-in-flash property	2019-10-28 07:47:28 -07:00
sifive_uart.c	riscv: hw: Remove the unnecessary include of target/riscv/cpu.h	2019-09-17 08:42:45 -07:00
spike.c	riscv: hw: Drop "clock-frequency" property of cpu nodes	2019-10-28 07:47:27 -07:00
trace-events
virt.c	RISC-V: virt: This is a "sifive,test1" test finisher	2019-11-25 12:34:52 -08:00