597f9b2d30
In preparation for returning the number of insns generated via the same pointer. Adjust only the prototypes so far. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
242 lines
7.3 KiB
C
242 lines
7.3 KiB
C
/*
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* Generic intermediate code generation.
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*
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* Copyright (C) 2016-2017 Lluís Vilanova <vilanova@ac.upc.edu>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#ifndef EXEC__TRANSLATOR_H
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#define EXEC__TRANSLATOR_H
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/*
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* Include this header from a target-specific file, and add a
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*
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* DisasContextBase base;
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*
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* member in your target-specific DisasContext.
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*/
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#include "qemu/bswap.h"
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#include "exec/exec-all.h"
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#include "exec/cpu_ldst.h"
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#include "exec/plugin-gen.h"
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#include "exec/translate-all.h"
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#include "tcg/tcg.h"
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/**
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* gen_intermediate_code
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* @cpu: cpu context
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* @tb: translation block
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* @max_insns: max number of instructions to translate
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* @pc: guest virtual program counter address
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* @host_pc: host physical program counter address
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*
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* This function must be provided by the target, which should create
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* the target-specific DisasContext, and then invoke translator_loop.
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*/
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void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
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target_ulong pc, void *host_pc);
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/**
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* DisasJumpType:
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* @DISAS_NEXT: Next instruction in program order.
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* @DISAS_TOO_MANY: Too many instructions translated.
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* @DISAS_NORETURN: Following code is dead.
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* @DISAS_TARGET_*: Start of target-specific conditions.
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*
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* What instruction to disassemble next.
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*/
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typedef enum DisasJumpType {
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DISAS_NEXT,
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DISAS_TOO_MANY,
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DISAS_NORETURN,
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DISAS_TARGET_0,
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DISAS_TARGET_1,
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DISAS_TARGET_2,
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DISAS_TARGET_3,
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DISAS_TARGET_4,
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DISAS_TARGET_5,
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DISAS_TARGET_6,
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DISAS_TARGET_7,
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DISAS_TARGET_8,
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DISAS_TARGET_9,
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DISAS_TARGET_10,
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DISAS_TARGET_11,
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} DisasJumpType;
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/**
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* DisasContextBase:
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* @tb: Translation block for this disassembly.
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* @pc_first: Address of first guest instruction in this TB.
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* @pc_next: Address of next guest instruction in this TB (current during
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* disassembly).
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* @is_jmp: What instruction to disassemble next.
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* @num_insns: Number of translated instructions (including current).
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* @max_insns: Maximum number of instructions to be translated in this TB.
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* @singlestep_enabled: "Hardware" single stepping enabled.
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*
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* Architecture-agnostic disassembly context.
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*/
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typedef struct DisasContextBase {
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TranslationBlock *tb;
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target_ulong pc_first;
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target_ulong pc_next;
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DisasJumpType is_jmp;
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int num_insns;
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int max_insns;
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bool singlestep_enabled;
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void *host_addr[2];
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} DisasContextBase;
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/**
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* TranslatorOps:
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* @init_disas_context:
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* Initialize the target-specific portions of DisasContext struct.
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* The generic DisasContextBase has already been initialized.
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*
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* @tb_start:
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* Emit any code required before the start of the main loop,
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* after the generic gen_tb_start().
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*
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* @insn_start:
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* Emit the tcg_gen_insn_start opcode.
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*
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* @translate_insn:
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* Disassemble one instruction and set db->pc_next for the start
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* of the following instruction. Set db->is_jmp as necessary to
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* terminate the main loop.
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*
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* @tb_stop:
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* Emit any opcodes required to exit the TB, based on db->is_jmp.
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*
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* @disas_log:
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* Print instruction disassembly to log.
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*/
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typedef struct TranslatorOps {
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void (*init_disas_context)(DisasContextBase *db, CPUState *cpu);
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void (*tb_start)(DisasContextBase *db, CPUState *cpu);
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void (*insn_start)(DisasContextBase *db, CPUState *cpu);
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void (*translate_insn)(DisasContextBase *db, CPUState *cpu);
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void (*tb_stop)(DisasContextBase *db, CPUState *cpu);
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void (*disas_log)(const DisasContextBase *db, CPUState *cpu, FILE *f);
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} TranslatorOps;
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/**
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* translator_loop:
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* @cpu: Target vCPU.
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* @tb: Translation block.
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* @max_insns: Maximum number of insns to translate.
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* @pc: guest virtual program counter address
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* @host_pc: host physical program counter address
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* @ops: Target-specific operations.
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* @db: Disassembly context.
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*
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* Generic translator loop.
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*
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* Translation will stop in the following cases (in order):
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* - When is_jmp set by #TranslatorOps::breakpoint_check.
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* - set to DISAS_TOO_MANY exits after translating one more insn
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* - set to any other value than DISAS_NEXT exits immediately.
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* - When is_jmp set by #TranslatorOps::translate_insn.
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* - set to any value other than DISAS_NEXT exits immediately.
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* - When the TCG operation buffer is full.
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* - When single-stepping is enabled (system-wide or on the current vCPU).
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* - When too many instructions have been translated.
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*/
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void translator_loop(CPUState *cpu, TranslationBlock *tb, int *max_insns,
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target_ulong pc, void *host_pc,
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const TranslatorOps *ops, DisasContextBase *db);
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void translator_loop_temp_check(DisasContextBase *db);
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/**
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* translator_use_goto_tb
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* @db: Disassembly context
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* @dest: target pc of the goto
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*
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* Return true if goto_tb is allowed between the current TB
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* and the destination PC.
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*/
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bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest);
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/*
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* Translator Load Functions
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*
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* These are intended to replace the direct usage of the cpu_ld*_code
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* functions and are mandatory for front-ends that have been migrated
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* to the common translator_loop. These functions are only intended
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* to be called from the translation stage and should not be called
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* from helper functions. Those functions should be converted to encode
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* the relevant information at translation time.
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*/
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uint8_t translator_ldub(CPUArchState *env, DisasContextBase *db, abi_ptr pc);
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uint16_t translator_lduw(CPUArchState *env, DisasContextBase *db, abi_ptr pc);
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uint32_t translator_ldl(CPUArchState *env, DisasContextBase *db, abi_ptr pc);
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uint64_t translator_ldq(CPUArchState *env, DisasContextBase *db, abi_ptr pc);
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static inline uint16_t
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translator_lduw_swap(CPUArchState *env, DisasContextBase *db,
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abi_ptr pc, bool do_swap)
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{
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uint16_t ret = translator_lduw(env, db, pc);
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if (do_swap) {
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ret = bswap16(ret);
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}
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return ret;
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}
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static inline uint32_t
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translator_ldl_swap(CPUArchState *env, DisasContextBase *db,
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abi_ptr pc, bool do_swap)
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{
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uint32_t ret = translator_ldl(env, db, pc);
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if (do_swap) {
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ret = bswap32(ret);
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}
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return ret;
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}
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static inline uint64_t
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translator_ldq_swap(CPUArchState *env, DisasContextBase *db,
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abi_ptr pc, bool do_swap)
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{
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uint64_t ret = translator_ldq(env, db, pc);
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if (do_swap) {
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ret = bswap64(ret);
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}
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return ret;
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}
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/**
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* translator_fake_ldb - fake instruction load
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* @insn8: byte of instruction
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* @pc: program counter of instruction
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*
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* This is a special case helper used where the instruction we are
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* about to translate comes from somewhere else (e.g. being
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* re-synthesised for s390x "ex"). It ensures we update other areas of
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* the translator with details of the executed instruction.
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*/
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static inline void translator_fake_ldb(uint8_t insn8, abi_ptr pc)
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{
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plugin_insn_append(pc, &insn8, sizeof(insn8));
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}
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/*
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* Return whether addr is on the same page as where disassembly started.
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* Translators can use this to enforce the rule that only single-insn
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* translation blocks are allowed to cross page boundaries.
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*/
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static inline bool is_same_page(const DisasContextBase *db, target_ulong addr)
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{
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return ((addr ^ db->pc_first) & TARGET_PAGE_MASK) == 0;
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}
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#endif /* EXEC__TRANSLATOR_H */
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