Cédric Le Goater 9bbdfe0569 aspeed/smc: Let the SSI core layer define the bus name ... If no id is provided, qdev automatically assigns an unique name with the following pattern "<type>.<index>" which avoids bus name collision when using multiple buses. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220307071856.1410731-6-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>		2022-03-08 09:18:11 +01:00
..
aspeed_smc.c	aspeed/smc: Let the SSI core layer define the bus name	2022-03-08 09:18:11 +01:00
imx_spi.c	hw/ssi: imx_spi: Correct tx and rx fifo endianness	2021-02-02 17:00:55 +00:00
Kconfig	hw/ssi: Add SiFive SPI controller support	2021-03-04 09:43:29 -05:00
meson.build	hw/ssi: Add a model of Xilinx Versal's OSPI flash memory controller	2022-01-28 14:29:46 +00:00
mss-spi.c	ssi: ssi_auto_connect_slaves() never does anything, drop	2020-06-15 22:05:28 +02:00
npcm7xx_fiu.c	hw/*: Use type casting for SysBusDevice in NPCM7XX	2021-01-12 21:19:02 +00:00
omap_spi.c	Include hw/irq.h a lot less	2019-08-16 13:31:52 +02:00
pl022.c	hw/ssi: Rename SSI 'slave' as 'peripheral'	2020-12-10 12:15:03 -05:00
sifive_spi.c	Do not include sysemu/sysemu.h if it's not really necessary	2021-05-02 17:24:50 +02:00
ssi.c	qbus: Rename qbus_create() to qbus_new()	2021-09-30 13:44:08 +01:00
stm32f2xx_spi.c	Include migration/vmstate.h less	2019-08-16 13:31:52 +02:00
trace-events	hw/ssi/npcm7xx_fiu: Fix handling of unsigned integer	2020-10-08 15:24:32 +01:00
trace.h	trace: switch position of headers to what Meson requires	2020-08-21 06:18:24 -04:00
xilinx_spi.c	hw: Do not include qemu/log.h if it is not necessary	2021-05-02 17:24:50 +02:00
xilinx_spips.c	hw/ssi: xilinx_spips: Remove DMA related dead codes from zynqmp_spips	2021-03-10 13:54:51 +00:00
xlnx-versal-ospi.c	migration: Remove load_state_old and minimum_version_id_old	2022-03-02 18:20:45 +00:00