24563a587f
This documents the overall XIVE architecture and the XIVE support for sPAPR guest machines (pseries). It also provides documentation on the 'info pic' command. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190521082411.24719-1-clg@kaod.org> Reviewed-by: Satheesh Rajendran <sathnaga@linux.vnet.ibm.com> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
200 lines
8.7 KiB
ReStructuredText
200 lines
8.7 KiB
ReStructuredText
================================
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POWER9 XIVE interrupt controller
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================================
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The POWER9 processor comes with a new interrupt controller
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architecture, called XIVE as "eXternal Interrupt Virtualization
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Engine".
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Compared to the previous architecture, the main characteristics of
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XIVE are to support a larger number of interrupt sources and to
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deliver interrupts directly to virtual processors without hypervisor
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assistance. This removes the context switches required for the
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delivery process.
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XIVE architecture
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=================
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The XIVE IC is composed of three sub-engines, each taking care of a
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processing layer of external interrupts:
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- Interrupt Virtualization Source Engine (IVSE), or Source Controller
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(SC). These are found in PCI PHBs, in the PSI host bridge
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controller, but also inside the main controller for the core IPIs
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and other sub-chips (NX, CAP, NPU) of the chip/processor. They are
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configured to feed the IVRE with events.
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- Interrupt Virtualization Routing Engine (IVRE) or Virtualization
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Controller (VC). It handles event coalescing and perform interrupt
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routing by matching an event source number with an Event
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Notification Descriptor (END).
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- Interrupt Virtualization Presentation Engine (IVPE) or Presentation
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Controller (PC). It maintains the interrupt context state of each
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thread and handles the delivery of the external interrupt to the
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thread.
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::
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XIVE Interrupt Controller
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+------------------------------------+ IPIs
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| +---------+ +---------+ +--------+ | +-------+
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| |IVRE | |Common Q | |IVPE |----> | CORES |
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| | esb | | | | |----> | |
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| | eas | | Bridge | | tctx |----> | |
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| |SC end | | | | nvt | | | |
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+------+ | +---------+ +----+----+ +--------+ | +-+-+-+-+
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| RAM | +------------------|-----------------+ | | |
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| | | | | |
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| | | | | |
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| | +--------------------v------------------------v-v-v--+ other
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| <--+ Power Bus +--> chips
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| esb | +---------+-----------------------+------------------+
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| eas | | |
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| end | +--|------+ |
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| nvt | +----+----+ | +----+----+
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+------+ |IVSE | | |IVSE |
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| | | | |
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| PQ-bits | | | PQ-bits |
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| local |-+ | in VC |
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+---------+ +---------+
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PCIe NX,NPU,CAPI
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PQ-bits: 2 bits source state machine (P:pending Q:queued)
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esb: Event State Buffer (Array of PQ bits in an IVSE)
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eas: Event Assignment Structure
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end: Event Notification Descriptor
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nvt: Notification Virtual Target
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tctx: Thread interrupt Context registers
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XIVE internal tables
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--------------------
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Each of the sub-engines uses a set of tables to redirect interrupts
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from event sources to CPU threads.
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::
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+-------+
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User or O/S | EQ |
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or +------>|entries|
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Hypervisor | | .. |
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Memory | +-------+
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| ^
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+-------------------------------------------------+
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Hypervisor +------+ +---+--+ +---+--+ +------+
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Memory | ESB | | EAT | | ENDT | | NVTT |
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(skiboot) +----+-+ +----+-+ +----+-+ +------+
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^ | ^ | ^ | ^
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+-------------------------------------------------+
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+----|--|--------|--|--------|--|-+ +-|-----+ +------+
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| | | | | | | | | | tctx| |Thread|
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IPI or ---+ + v + v + v |---| + .. |-----> |
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HW events | | | | | |
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| IVRE | | IVPE | +------+
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+---------------------------------+ +-------+
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The IVSE have a 2-bits state machine, P for pending and Q for queued,
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for each source that allows events to be triggered. They are stored in
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an Event State Buffer (ESB) array and can be controlled by MMIOs.
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If the event is let through, the IVRE looks up in the Event Assignment
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Structure (EAS) table for an Event Notification Descriptor (END)
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configured for the source. Each Event Notification Descriptor defines
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a notification path to a CPU and an in-memory Event Queue, in which
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will be enqueued an EQ data for the O/S to pull.
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The IVPE determines if a Notification Virtual Target (NVT) can handle
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the event by scanning the thread contexts of the VCPUs dispatched on
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the processor HW threads. It maintains the interrupt context state of
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each thread in a NVT table.
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XIVE thread interrupt context
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-----------------------------
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The XIVE presenter can generate four different exceptions to its
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HW threads:
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- hypervisor exception
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- O/S exception
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- Event-Based Branch (user level)
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- msgsnd (doorbell)
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Each exception has a state independent from the others called a Thread
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Interrupt Management context. This context is a set of registers which
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lets the thread handle priority management and interrupt
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acknowledgment among other things. The most important ones being :
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- Interrupt Priority Register (PIPR)
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- Interrupt Pending Buffer (IPB)
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- Current Processor Priority (CPPR)
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- Notification Source Register (NSR)
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TIMA
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~~~~
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The Thread Interrupt Management registers are accessible through a
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specific MMIO region, called the Thread Interrupt Management Area
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(TIMA), four aligned pages, each exposing a different view of the
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registers. First page (page address ending in ``0b00``) gives access
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to the entire context and is reserved for the ring 0 view for the
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physical thread context. The second (page address ending in ``0b01``)
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is for the hypervisor, ring 1 view. The third (page address ending in
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``0b10``) is for the operating system, ring 2 view. The fourth (page
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address ending in ``0b11``) is for user level, ring 3 view.
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Interrupt flow from an O/S perspective
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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After an event data has been enqueued in the O/S Event Queue, the IVPE
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raises the bit corresponding to the priority of the pending interrupt
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in the register IBP (Interrupt Pending Buffer) to indicate that an
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event is pending in one of the 8 priority queues. The Pending
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Interrupt Priority Register (PIPR) is also updated using the IPB. This
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register represent the priority of the most favored pending
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notification.
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The PIPR is then compared to the the Current Processor Priority
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Register (CPPR). If it is more favored (numerically less than), the
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CPU interrupt line is raised and the EO bit of the Notification Source
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Register (NSR) is updated to notify the presence of an exception for
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the O/S. The O/S acknowledges the interrupt with a special load in the
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Thread Interrupt Management Area.
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The O/S handles the interrupt and when done, performs an EOI using a
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MMIO operation on the ESB management page of the associate source.
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Overview of the QEMU models for XIVE
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====================================
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The XiveSource models the IVSE in general, internal and external. It
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handles the source ESBs and the MMIO interface to control them.
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The XiveNotifier is a small helper interface interconnecting the
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XiveSource to the XiveRouter.
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The XiveRouter is an abstract model acting as a combined IVRE and
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IVPE. It routes event notifications using the EAS and END tables to
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the IVPE sub-engine which does a CAM scan to find a CPU to deliver the
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exception. Storage should be provided by the inheriting classes.
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XiveEnDSource is a special source object. It exposes the END ESB MMIOs
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of the Event Queues which are used for coalescing event notifications
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and for escalation. Not used on the field, only to sync the EQ cache
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in OPAL.
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Finally, the XiveTCTX contains the interrupt state context of a thread,
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four sets of registers, one for each exception that can be delivered
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to a CPU. These contexts are scanned by the IVPE to find a matching VP
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when a notification is triggered. It also models the Thread Interrupt
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Management Area (TIMA), which exposes the thread context registers to
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the CPU for interrupt management.
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