0c8e6ac989
The test in tests/avocado/machine_loongarch.py is currently failing
on big endian hosts like s390x. By comparing the traces between running
the QEMU_EFI.fd bios on a s390x and on a x86 host, it's quickly obvious
that the CSRRD instruction for the CPUID is behaving differently. And
indeed: The code currently does a long read (i.e. 64 bit) from the
address that points to the CPUState->cpu_index field (with tcg_gen_ld_tl()
in the trans_csrrd() function). But this cpu_index field is only an "int"
(i.e. 32 bit). While this dirty pointer magic works on little endian hosts,
it of course fails on big endian hosts. Fix it by using a proper helper
function instead.
Message-Id: <20230720175307.854460-1-thuth@redhat.com>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Thomas Huth <thuth@redhat.com>
(cherry picked from commit c34ad45992)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
425 lines
11 KiB
C
425 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* QEMU LoongArch CPU
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*
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* Copyright (c) 2021 Loongson Technology Corporation Limited
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*/
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#ifndef LOONGARCH_CPU_H
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#define LOONGARCH_CPU_H
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#include "exec/cpu-defs.h"
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#include "fpu/softfloat-types.h"
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#include "hw/registerfields.h"
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#include "qemu/timer.h"
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#include "exec/memory.h"
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#include "hw/sysbus.h"
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#include "cpu-csr.h"
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#define IOCSRF_TEMP 0
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#define IOCSRF_NODECNT 1
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#define IOCSRF_MSI 2
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#define IOCSRF_EXTIOI 3
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#define IOCSRF_CSRIPI 4
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#define IOCSRF_FREQCSR 5
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#define IOCSRF_FREQSCALE 6
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#define IOCSRF_DVFSV1 7
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#define IOCSRF_GMOD 9
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#define IOCSRF_VM 11
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#define FEATURE_REG 0x8
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#define VENDOR_REG 0x10
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#define CPUNAME_REG 0x20
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#define MISC_FUNC_REG 0x420
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#define IOCSRM_EXTIOI_EN 48
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#define IOCSR_MEM_SIZE 0x428
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#define TCG_GUEST_DEFAULT_MO (0)
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#define FCSR0_M1 0x1f /* FCSR1 mask, Enables */
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#define FCSR0_M2 0x1f1f0000 /* FCSR2 mask, Cause and Flags */
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#define FCSR0_M3 0x300 /* FCSR3 mask, Round Mode */
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#define FCSR0_RM 8 /* Round Mode bit num on fcsr0 */
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FIELD(FCSR0, ENABLES, 0, 5)
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FIELD(FCSR0, RM, 8, 2)
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FIELD(FCSR0, FLAGS, 16, 5)
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FIELD(FCSR0, CAUSE, 24, 5)
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#define GET_FP_CAUSE(REG) FIELD_EX32(REG, FCSR0, CAUSE)
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#define SET_FP_CAUSE(REG, V) \
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do { \
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(REG) = FIELD_DP32(REG, FCSR0, CAUSE, V); \
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} while (0)
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#define GET_FP_ENABLES(REG) FIELD_EX32(REG, FCSR0, ENABLES)
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#define SET_FP_ENABLES(REG, V) \
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do { \
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(REG) = FIELD_DP32(REG, FCSR0, ENABLES, V); \
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} while (0)
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#define GET_FP_FLAGS(REG) FIELD_EX32(REG, FCSR0, FLAGS)
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#define SET_FP_FLAGS(REG, V) \
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do { \
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(REG) = FIELD_DP32(REG, FCSR0, FLAGS, V); \
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} while (0)
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#define UPDATE_FP_FLAGS(REG, V) \
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do { \
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(REG) |= FIELD_DP32(0, FCSR0, FLAGS, V); \
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} while (0)
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#define FP_INEXACT 1
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#define FP_UNDERFLOW 2
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#define FP_OVERFLOW 4
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#define FP_DIV0 8
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#define FP_INVALID 16
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#define EXCODE(code, subcode) ( ((subcode) << 6) | (code) )
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#define EXCODE_MCODE(code) ( (code) & 0x3f )
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#define EXCODE_SUBCODE(code) ( (code) >> 6 )
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#define EXCCODE_EXTERNAL_INT 64 /* plus external interrupt number */
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#define EXCCODE_INT EXCODE(0, 0)
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#define EXCCODE_PIL EXCODE(1, 0)
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#define EXCCODE_PIS EXCODE(2, 0)
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#define EXCCODE_PIF EXCODE(3, 0)
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#define EXCCODE_PME EXCODE(4, 0)
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#define EXCCODE_PNR EXCODE(5, 0)
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#define EXCCODE_PNX EXCODE(6, 0)
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#define EXCCODE_PPI EXCODE(7, 0)
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#define EXCCODE_ADEF EXCODE(8, 0) /* Different exception subcode */
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#define EXCCODE_ADEM EXCODE(8, 1)
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#define EXCCODE_ALE EXCODE(9, 0)
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#define EXCCODE_BCE EXCODE(10, 0)
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#define EXCCODE_SYS EXCODE(11, 0)
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#define EXCCODE_BRK EXCODE(12, 0)
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#define EXCCODE_INE EXCODE(13, 0)
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#define EXCCODE_IPE EXCODE(14, 0)
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#define EXCCODE_FPD EXCODE(15, 0)
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#define EXCCODE_SXD EXCODE(16, 0)
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#define EXCCODE_ASXD EXCODE(17, 0)
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#define EXCCODE_FPE EXCODE(18, 0) /* Different exception subcode */
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#define EXCCODE_VFPE EXCODE(18, 1)
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#define EXCCODE_WPEF EXCODE(19, 0) /* Different exception subcode */
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#define EXCCODE_WPEM EXCODE(19, 1)
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#define EXCCODE_BTD EXCODE(20, 0)
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#define EXCCODE_BTE EXCODE(21, 0)
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#define EXCCODE_DBP EXCODE(26, 0) /* Reserved subcode used for debug */
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/* cpucfg[0] bits */
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FIELD(CPUCFG0, PRID, 0, 32)
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/* cpucfg[1] bits */
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FIELD(CPUCFG1, ARCH, 0, 2)
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FIELD(CPUCFG1, PGMMU, 2, 1)
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FIELD(CPUCFG1, IOCSR, 3, 1)
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FIELD(CPUCFG1, PALEN, 4, 8)
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FIELD(CPUCFG1, VALEN, 12, 8)
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FIELD(CPUCFG1, UAL, 20, 1)
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FIELD(CPUCFG1, RI, 21, 1)
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FIELD(CPUCFG1, EP, 22, 1)
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FIELD(CPUCFG1, RPLV, 23, 1)
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FIELD(CPUCFG1, HP, 24, 1)
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FIELD(CPUCFG1, IOCSR_BRD, 25, 1)
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FIELD(CPUCFG1, MSG_INT, 26, 1)
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/* cpucfg[2] bits */
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FIELD(CPUCFG2, FP, 0, 1)
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FIELD(CPUCFG2, FP_SP, 1, 1)
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FIELD(CPUCFG2, FP_DP, 2, 1)
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FIELD(CPUCFG2, FP_VER, 3, 3)
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FIELD(CPUCFG2, LSX, 6, 1)
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FIELD(CPUCFG2, LASX, 7, 1)
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FIELD(CPUCFG2, COMPLEX, 8, 1)
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FIELD(CPUCFG2, CRYPTO, 9, 1)
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FIELD(CPUCFG2, LVZ, 10, 1)
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FIELD(CPUCFG2, LVZ_VER, 11, 3)
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FIELD(CPUCFG2, LLFTP, 14, 1)
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FIELD(CPUCFG2, LLFTP_VER, 15, 3)
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FIELD(CPUCFG2, LBT_X86, 18, 1)
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FIELD(CPUCFG2, LBT_ARM, 19, 1)
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FIELD(CPUCFG2, LBT_MIPS, 20, 1)
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FIELD(CPUCFG2, LSPW, 21, 1)
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FIELD(CPUCFG2, LAM, 22, 1)
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/* cpucfg[3] bits */
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FIELD(CPUCFG3, CCDMA, 0, 1)
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FIELD(CPUCFG3, SFB, 1, 1)
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FIELD(CPUCFG3, UCACC, 2, 1)
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FIELD(CPUCFG3, LLEXC, 3, 1)
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FIELD(CPUCFG3, SCDLY, 4, 1)
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FIELD(CPUCFG3, LLDBAR, 5, 1)
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FIELD(CPUCFG3, ITLBHMC, 6, 1)
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FIELD(CPUCFG3, ICHMC, 7, 1)
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FIELD(CPUCFG3, SPW_LVL, 8, 3)
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FIELD(CPUCFG3, SPW_HP_HF, 11, 1)
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FIELD(CPUCFG3, RVA, 12, 1)
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FIELD(CPUCFG3, RVAMAX, 13, 4)
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/* cpucfg[4] bits */
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FIELD(CPUCFG4, CC_FREQ, 0, 32)
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/* cpucfg[5] bits */
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FIELD(CPUCFG5, CC_MUL, 0, 16)
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FIELD(CPUCFG5, CC_DIV, 16, 16)
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/* cpucfg[6] bits */
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FIELD(CPUCFG6, PMP, 0, 1)
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FIELD(CPUCFG6, PMVER, 1, 3)
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FIELD(CPUCFG6, PMNUM, 4, 4)
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FIELD(CPUCFG6, PMBITS, 8, 6)
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FIELD(CPUCFG6, UPM, 14, 1)
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/* cpucfg[16] bits */
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FIELD(CPUCFG16, L1_IUPRE, 0, 1)
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FIELD(CPUCFG16, L1_IUUNIFY, 1, 1)
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FIELD(CPUCFG16, L1_DPRE, 2, 1)
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FIELD(CPUCFG16, L2_IUPRE, 3, 1)
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FIELD(CPUCFG16, L2_IUUNIFY, 4, 1)
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FIELD(CPUCFG16, L2_IUPRIV, 5, 1)
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FIELD(CPUCFG16, L2_IUINCL, 6, 1)
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FIELD(CPUCFG16, L2_DPRE, 7, 1)
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FIELD(CPUCFG16, L2_DPRIV, 8, 1)
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FIELD(CPUCFG16, L2_DINCL, 9, 1)
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FIELD(CPUCFG16, L3_IUPRE, 10, 1)
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FIELD(CPUCFG16, L3_IUUNIFY, 11, 1)
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FIELD(CPUCFG16, L3_IUPRIV, 12, 1)
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FIELD(CPUCFG16, L3_IUINCL, 13, 1)
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FIELD(CPUCFG16, L3_DPRE, 14, 1)
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FIELD(CPUCFG16, L3_DPRIV, 15, 1)
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FIELD(CPUCFG16, L3_DINCL, 16, 1)
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/* cpucfg[17] bits */
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FIELD(CPUCFG17, L1IU_WAYS, 0, 16)
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FIELD(CPUCFG17, L1IU_SETS, 16, 8)
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FIELD(CPUCFG17, L1IU_SIZE, 24, 7)
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/* cpucfg[18] bits */
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FIELD(CPUCFG18, L1D_WAYS, 0, 16)
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FIELD(CPUCFG18, L1D_SETS, 16, 8)
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FIELD(CPUCFG18, L1D_SIZE, 24, 7)
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/* cpucfg[19] bits */
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FIELD(CPUCFG19, L2IU_WAYS, 0, 16)
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FIELD(CPUCFG19, L2IU_SETS, 16, 8)
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FIELD(CPUCFG19, L2IU_SIZE, 24, 7)
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/* cpucfg[20] bits */
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FIELD(CPUCFG20, L3IU_WAYS, 0, 16)
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FIELD(CPUCFG20, L3IU_SETS, 16, 8)
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FIELD(CPUCFG20, L3IU_SIZE, 24, 7)
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/*CSR_CRMD */
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FIELD(CSR_CRMD, PLV, 0, 2)
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FIELD(CSR_CRMD, IE, 2, 1)
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FIELD(CSR_CRMD, DA, 3, 1)
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FIELD(CSR_CRMD, PG, 4, 1)
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FIELD(CSR_CRMD, DATF, 5, 2)
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FIELD(CSR_CRMD, DATM, 7, 2)
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FIELD(CSR_CRMD, WE, 9, 1)
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extern const char * const regnames[32];
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extern const char * const fregnames[32];
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#define N_IRQS 13
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#define IRQ_TIMER 11
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#define IRQ_IPI 12
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#define LOONGARCH_STLB 2048 /* 2048 STLB */
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#define LOONGARCH_MTLB 64 /* 64 MTLB */
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#define LOONGARCH_TLB_MAX (LOONGARCH_STLB + LOONGARCH_MTLB)
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/*
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* define the ASID PS E VPPN field of TLB
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*/
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FIELD(TLB_MISC, E, 0, 1)
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FIELD(TLB_MISC, ASID, 1, 10)
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FIELD(TLB_MISC, VPPN, 13, 35)
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FIELD(TLB_MISC, PS, 48, 6)
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struct LoongArchTLB {
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uint64_t tlb_misc;
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/* Fields corresponding to CSR_TLBELO0/1 */
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uint64_t tlb_entry0;
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uint64_t tlb_entry1;
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};
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typedef struct LoongArchTLB LoongArchTLB;
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typedef struct CPUArchState {
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uint64_t gpr[32];
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uint64_t pc;
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uint64_t fpr[32];
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float_status fp_status;
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bool cf[8];
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uint32_t fcsr0;
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uint32_t fcsr0_mask;
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uint32_t cpucfg[21];
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uint64_t lladdr; /* LL virtual address compared against SC */
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uint64_t llval;
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/* LoongArch CSRs */
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uint64_t CSR_CRMD;
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uint64_t CSR_PRMD;
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uint64_t CSR_EUEN;
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uint64_t CSR_MISC;
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uint64_t CSR_ECFG;
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uint64_t CSR_ESTAT;
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uint64_t CSR_ERA;
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uint64_t CSR_BADV;
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uint64_t CSR_BADI;
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uint64_t CSR_EENTRY;
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uint64_t CSR_TLBIDX;
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uint64_t CSR_TLBEHI;
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uint64_t CSR_TLBELO0;
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uint64_t CSR_TLBELO1;
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uint64_t CSR_ASID;
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uint64_t CSR_PGDL;
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uint64_t CSR_PGDH;
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uint64_t CSR_PGD;
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uint64_t CSR_PWCL;
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uint64_t CSR_PWCH;
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uint64_t CSR_STLBPS;
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uint64_t CSR_RVACFG;
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uint64_t CSR_PRCFG1;
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uint64_t CSR_PRCFG2;
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uint64_t CSR_PRCFG3;
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uint64_t CSR_SAVE[16];
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uint64_t CSR_TID;
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uint64_t CSR_TCFG;
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uint64_t CSR_TVAL;
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uint64_t CSR_CNTC;
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uint64_t CSR_TICLR;
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uint64_t CSR_LLBCTL;
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uint64_t CSR_IMPCTL1;
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uint64_t CSR_IMPCTL2;
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uint64_t CSR_TLBRENTRY;
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uint64_t CSR_TLBRBADV;
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uint64_t CSR_TLBRERA;
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uint64_t CSR_TLBRSAVE;
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uint64_t CSR_TLBRELO0;
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uint64_t CSR_TLBRELO1;
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uint64_t CSR_TLBREHI;
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uint64_t CSR_TLBRPRMD;
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uint64_t CSR_MERRCTL;
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uint64_t CSR_MERRINFO1;
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uint64_t CSR_MERRINFO2;
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uint64_t CSR_MERRENTRY;
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uint64_t CSR_MERRERA;
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uint64_t CSR_MERRSAVE;
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uint64_t CSR_CTAG;
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uint64_t CSR_DMW[4];
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uint64_t CSR_DBG;
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uint64_t CSR_DERA;
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uint64_t CSR_DSAVE;
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uint64_t CSR_CPUID;
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#ifndef CONFIG_USER_ONLY
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LoongArchTLB tlb[LOONGARCH_TLB_MAX];
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AddressSpace address_space_iocsr;
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MemoryRegion system_iocsr;
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MemoryRegion iocsr_mem;
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bool load_elf;
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uint64_t elf_address;
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#endif
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} CPULoongArchState;
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/**
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* LoongArchCPU:
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* @env: #CPULoongArchState
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*
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* A LoongArch CPU.
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*/
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struct ArchCPU {
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/*< private >*/
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CPUState parent_obj;
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/*< public >*/
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CPUNegativeOffsetState neg;
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CPULoongArchState env;
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QEMUTimer timer;
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/* 'compatible' string for this CPU for Linux device trees */
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const char *dtb_compatible;
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};
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#define TYPE_LOONGARCH_CPU "loongarch-cpu"
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OBJECT_DECLARE_CPU_TYPE(LoongArchCPU, LoongArchCPUClass,
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LOONGARCH_CPU)
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/**
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* LoongArchCPUClass:
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* @parent_realize: The parent class' realize handler.
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* @parent_reset: The parent class' reset handler.
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*
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* A LoongArch CPU model.
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*/
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struct LoongArchCPUClass {
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/*< private >*/
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CPUClass parent_class;
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/*< public >*/
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DeviceRealize parent_realize;
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DeviceReset parent_reset;
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};
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/*
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* LoongArch CPUs has 4 privilege levels.
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* 0 for kernel mode, 3 for user mode.
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* Define an extra index for DA(direct addressing) mode.
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*/
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#define MMU_PLV_KERNEL 0
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#define MMU_PLV_USER 3
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#define MMU_IDX_KERNEL MMU_PLV_KERNEL
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#define MMU_IDX_USER MMU_PLV_USER
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#define MMU_IDX_DA 4
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static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch)
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{
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#ifdef CONFIG_USER_ONLY
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return MMU_IDX_USER;
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#else
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if (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG)) {
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return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV);
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}
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return MMU_IDX_DA;
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#endif
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}
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/*
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* LoongArch CPUs hardware flags.
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*/
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#define HW_FLAGS_PLV_MASK R_CSR_CRMD_PLV_MASK /* 0x03 */
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#define HW_FLAGS_CRMD_PG R_CSR_CRMD_PG_MASK /* 0x10 */
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#define HW_FLAGS_EUEN_FPE 0x04
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static inline void cpu_get_tb_cpu_state(CPULoongArchState *env,
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target_ulong *pc,
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target_ulong *cs_base,
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uint32_t *flags)
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{
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*pc = env->pc;
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*cs_base = 0;
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*flags = env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK);
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*flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FPE;
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}
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void loongarch_cpu_list(void);
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#define cpu_list loongarch_cpu_list
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#include "exec/cpu-all.h"
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#define LOONGARCH_CPU_TYPE_SUFFIX "-" TYPE_LOONGARCH_CPU
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#define LOONGARCH_CPU_TYPE_NAME(model) model LOONGARCH_CPU_TYPE_SUFFIX
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#define CPU_RESOLVING_TYPE TYPE_LOONGARCH_CPU
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#endif /* LOONGARCH_CPU_H */
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