ec150c7e09
Back in 2016, we discussed[1] rules for headers, and these were
generally liked:
1. Have a carefully curated header that's included everywhere first. We
got that already thanks to Peter: osdep.h.
2. Headers should normally include everything they need beyond osdep.h.
If exceptions are needed for some reason, they must be documented in
the header. If all that's needed from a header is typedefs, put
those into qemu/typedefs.h instead of including the header.
3. Cyclic inclusion is forbidden.
This patch gets include/ closer to obeying 2.
It's actually extracted from my "[RFC] Baby steps towards saner
headers" series[2], which demonstrates a possible path towards
checking 2 automatically. It passes the RFC test there.
[1] Message-ID: <87h9g8j57d.fsf@blackfin.pond.sub.org>
https://lists.nongnu.org/archive/html/qemu-devel/2016-03/msg03345.html
[2] Message-Id: <20190711122827.18970-1-armbru@redhat.com>
https://lists.nongnu.org/archive/html/qemu-devel/2019-07/msg02715.html
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20190812052359.30071-2-armbru@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
92 lines
2.6 KiB
C
92 lines
2.6 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2015 Imagination Technologies
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*
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*/
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#ifndef MIPS_CMGCR_H
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#define MIPS_CMGCR_H
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#include "hw/sysbus.h"
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#define TYPE_MIPS_GCR "mips-gcr"
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#define MIPS_GCR(obj) OBJECT_CHECK(MIPSGCRState, (obj), TYPE_MIPS_GCR)
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#define GCR_BASE_ADDR 0x1fbf8000ULL
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#define GCR_ADDRSPACE_SZ 0x8000
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/* Offsets to register blocks */
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#define MIPS_GCB_OFS 0x0000 /* Global Control Block */
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#define MIPS_CLCB_OFS 0x2000 /* Core Local Control Block */
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#define MIPS_COCB_OFS 0x4000 /* Core Other Control Block */
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#define MIPS_GDB_OFS 0x6000 /* Global Debug Block */
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/* Global Control Block Register Map */
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#define GCR_CONFIG_OFS 0x0000
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#define GCR_BASE_OFS 0x0008
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#define GCR_REV_OFS 0x0030
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#define GCR_GIC_BASE_OFS 0x0080
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#define GCR_CPC_BASE_OFS 0x0088
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#define GCR_GIC_STATUS_OFS 0x00D0
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#define GCR_CPC_STATUS_OFS 0x00F0
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#define GCR_L2_CONFIG_OFS 0x0130
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/* Core Local and Core Other Block Register Map */
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#define GCR_CL_CONFIG_OFS 0x0010
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#define GCR_CL_OTHER_OFS 0x0018
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#define GCR_CL_RESETBASE_OFS 0x0020
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/* GCR_L2_CONFIG register fields */
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#define GCR_L2_CONFIG_BYPASS_SHF 20
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#define GCR_L2_CONFIG_BYPASS_MSK ((0x1ULL) << GCR_L2_CONFIG_BYPASS_SHF)
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/* GCR_BASE register fields */
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#define GCR_BASE_GCRBASE_MSK 0xffffffff8000ULL
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/* GCR_GIC_BASE register fields */
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#define GCR_GIC_BASE_GICEN_MSK 1
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#define GCR_GIC_BASE_GICBASE_MSK 0xFFFFFFFE0000ULL
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#define GCR_GIC_BASE_MSK (GCR_GIC_BASE_GICEN_MSK | GCR_GIC_BASE_GICBASE_MSK)
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/* GCR_CPC_BASE register fields */
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#define GCR_CPC_BASE_CPCEN_MSK 1
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#define GCR_CPC_BASE_CPCBASE_MSK 0xFFFFFFFF8000ULL
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#define GCR_CPC_BASE_MSK (GCR_CPC_BASE_CPCEN_MSK | GCR_CPC_BASE_CPCBASE_MSK)
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/* GCR_CL_OTHER_OFS register fields */
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#define GCR_CL_OTHER_VPOTHER_MSK 0x7
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#define GCR_CL_OTHER_MSK GCR_CL_OTHER_VPOTHER_MSK
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/* GCR_CL_RESETBASE_OFS register fields */
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#define GCR_CL_RESET_BASE_RESETBASE_MSK 0xFFFFF000U
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#define GCR_CL_RESET_BASE_MSK GCR_CL_RESET_BASE_RESETBASE_MSK
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typedef struct MIPSGCRVPState MIPSGCRVPState;
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struct MIPSGCRVPState {
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uint32_t other;
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uint64_t reset_base;
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};
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typedef struct MIPSGCRState MIPSGCRState;
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struct MIPSGCRState {
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SysBusDevice parent_obj;
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int32_t gcr_rev;
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int32_t num_vps;
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hwaddr gcr_base;
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MemoryRegion iomem;
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MemoryRegion *cpc_mr;
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MemoryRegion *gic_mr;
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uint64_t cpc_base;
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uint64_t gic_base;
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/* VP Local/Other Registers */
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MIPSGCRVPState *vps;
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};
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#endif /* MIPS_CMGCR_H */
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