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Peter Maydell 9740b907a5 target-arm queue: 
* cleanups of qemu_oom_check() and qemu_memalign()
  * target/arm/translate-neon: UNDEF if VLD1/VST1 stride bits are non-zero
  * target/arm/translate-neon: Simplify align field check for VLD3
  * GICv3 ITS: add more trace events
  * GICv3 ITS: implement 8-byte accesses properly
  * GICv3: fix minor issues with some trace/log messages
  * ui/cocoa: Use the standard about panel
  * target/arm: Provide cpu property for controling FEAT_LPA2
  * hw/arm/virt: Disable LPA2 for -machine virt-6.2
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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20220307' into staging

target-arm queue:
 * cleanups of qemu_oom_check() and qemu_memalign()
 * target/arm/translate-neon: UNDEF if VLD1/VST1 stride bits are non-zero
 * target/arm/translate-neon: Simplify align field check for VLD3
 * GICv3 ITS: add more trace events
 * GICv3 ITS: implement 8-byte accesses properly
 * GICv3: fix minor issues with some trace/log messages
 * ui/cocoa: Use the standard about panel
 * target/arm: Provide cpu property for controling FEAT_LPA2
 * hw/arm/virt: Disable LPA2 for -machine virt-6.2

# gpg: Signature made Mon 07 Mar 2022 16:46:06 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20220307:
  hw/arm/virt: Disable LPA2 for -machine virt-6.2
  target/arm: Provide cpu property for controling FEAT_LPA2
  ui/cocoa: Use the standard about panel
  hw/intc/arm_gicv3_cpuif: Fix register names in ICV_HPPIR read trace event
  hw/intc/arm_gicv3: Fix missing spaces in error log messages
  hw/intc/arm_gicv3: Specify valid and impl in MemoryRegionOps
  hw/intc/arm_gicv3_its: Add trace events for table reads and writes
  hw/intc/arm_gicv3_its: Add trace events for commands
  target/arm/translate-neon: Simplify align field check for VLD3
  target/arm/translate-neon: UNDEF if VLD1/VST1 stride bits are non-zero
  osdep: Move memalign-related functions to their own header
  util: Put qemu_vfree() in memalign.c
  util: Use meson checks for valloc() and memalign() presence
  util: Share qemu_try_memalign() implementation between POSIX and Windows
  meson.build: Don't misdetect posix_memalign() on Windows
  util: Return valid allocation for qemu_try_memalign() with zero size
  util: Unify implementations of qemu_memalign()
  util: Make qemu_oom_check() a static function

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-03-08 15:26:10 +00:00
..
alpha target: Use ArchCPU as interface to target CPU 2022-03-06 22:23:09 +01:00
arm target-arm queue: 2022-03-08 15:26:10 +00:00
avr target: Use ArchCPU as interface to target CPU 2022-03-06 22:23:09 +01:00
cris target: Use ArchCPU as interface to target CPU 2022-03-06 22:23:09 +01:00
hexagon target: Use ArchCPU as interface to target CPU 2022-03-06 22:23:09 +01:00
hppa target: Use ArchCPU as interface to target CPU 2022-03-06 22:23:09 +01:00
i386 target-arm queue: 2022-03-08 15:26:10 +00:00
m68k target: Use ArchCPU as interface to target CPU 2022-03-06 22:23:09 +01:00
microblaze target: Use ArchCPU as interface to target CPU 2022-03-06 22:23:09 +01:00
mips target: Use ArchCPU as interface to target CPU 2022-03-06 22:23:09 +01:00
nios2 target: Use ArchCPU as interface to target CPU 2022-03-06 22:23:09 +01:00
openrisc target: Use ArchCPU as interface to target CPU 2022-03-06 22:23:09 +01:00
ppc target: Use ArchCPU as interface to target CPU 2022-03-06 22:23:09 +01:00
riscv target: Use ArchCPU as interface to target CPU 2022-03-06 22:23:09 +01:00
rx target: Use ArchCPU as interface to target CPU 2022-03-06 22:23:09 +01:00
s390x target: Use ArchCPU as interface to target CPU 2022-03-06 22:23:09 +01:00
sh4 target: Use ArchCPU as interface to target CPU 2022-03-06 22:23:09 +01:00
sparc target: Use ArchCPU as interface to target CPU 2022-03-06 22:23:09 +01:00
tricore target: Use ArchCPU as interface to target CPU 2022-03-06 22:23:09 +01:00
xtensa target: Use ArchCPU as interface to target CPU 2022-03-06 22:23:09 +01:00
Kconfig meson: Introduce target-specific Kconfig 2021-07-09 18:21:34 +02:00
meson.build