Peter Maydell 99ae0cd90d target-arm queue: ... * hw/intc/arm_gic: Allow to use QTest without crashing * hw/char/exynos4210_uart: Fix buffer size reporting with FIFO disabled * hw/char/exynos4210_uart: Fix missing call to report ready for input * hw/arm/smmuv3: Fix addr_mask for range-based invalidation * hw/ssi/imx_spi: Fix various minor bugs * hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register * hw/arm: Add missing Kconfig dependencies * hw/arm: Display CPU type in machine description -----BEGIN PGP SIGNATURE----- iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmAaeAQZHHBldGVyLm1h eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3tWFD/9VTSSTmGMtSLGpuVt6t07x zqaFvRe+xUjrunwt25yx9tu9o4txXTk6mekgAz51QSeijESVIQQUKArZjbLWxRjl EXZAedOCF+f+lpzdQCO/GZtsHOfcWa158qm51NlEIM3cn1NiSASs0ky3r52MjjAR g0NFYTiZNplq8ah/0RljhHMhnAHzUbp/IErIxknWOVKvaH45+eji7mKxUk2vaCXB L5HCEzGCbPCqMMi3DFcwm9nNIYRu7X0hs9nR0AXTvdXbCoDqSyD4dEpjEcK/2IFM 4zbS4NFRD7ndjD0C502+EUFav3tfd5/UfIjNg3oquMTDQrMCvh5Y1i3II0lVVWe5 eSfbqV2eBzJHBanf7P64fRpk9mBNduJ8BZrozICvkCJxj5y3nTofKA9hXeGaDAdy 7sA7Uzkpb1vnnMFzYk/0t2D6BSSFiknYuDHnfMY0nRoHsuDvY5yHw9Tt181D+qST UyLcmS8BB227WGgQPKSsFiUu7U423BIoiD5pp8cRyAg+FojqH6BZrcVluUWng6Ru ZVG0349lTmZ4mgv2hZI1qqIh80o40TI6K7OerQuMkZlq+4xseZvyb6+SQHaQ/j3I CKBiN15y/UzE5eivG6Siq3MR2myCBCSevTxDw4s+zR9FhoRQqFKoDhPGXTR9btWo 1mgDNUQfyWtCcdoJKb7jEg== =kWoi -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210203' into staging target-arm queue: * hw/intc/arm_gic: Allow to use QTest without crashing * hw/char/exynos4210_uart: Fix buffer size reporting with FIFO disabled * hw/char/exynos4210_uart: Fix missing call to report ready for input * hw/arm/smmuv3: Fix addr_mask for range-based invalidation * hw/ssi/imx_spi: Fix various minor bugs * hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register * hw/arm: Add missing Kconfig dependencies * hw/arm: Display CPU type in machine description # gpg: Signature made Wed 03 Feb 2021 10:16:36 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20210203: (21 commits) hw/arm: Display CPU type in machine description hw/net/can: ZynqMP CAN device requires PTIMER hw/arm/xlnx-versal: Versal SoC requires ZynqMP peripherals hw/arm/xlnx-versal: Versal SoC requires ZDMA hw/arm/exynos4210: Add missing dependency on OR_IRQ hw/arm/stm32f405_soc: Add missing dependency on OR_IRQ hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register hw/ssi: imx_spi: Correct tx and rx fifo endianness hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic hw/ssi: imx_spi: Round up the burst length to be multiple of 8 hw/ssi: imx_spi: Disable chip selects when controller is disabled hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value hw/ssi: imx_spi: Remove pointless variable initialization hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset() hw/ssi: imx_spi: Use a macro for number of chip selects supported hw/arm/smmuv3: Fix addr_mask for range-based invalidation hw/char/exynos4210_uart: Fix missing call to report ready for input hw/char/exynos4210_uart: Fix buffer size reporting with FIFO disabled ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>		2021-02-03 12:55:44 +00:00
..
authz	Prefer 'on' | 'off' over 'yes' | 'no' for bool options	2021-01-29 17:07:53 +00:00
block	block/block-copy: drop unused argument of block_copy()	2021-01-26 14:36:37 +01:00
chardev	chardev: do not use machine_init_done	2020-12-15 12:51:51 -05:00
crypto	qom: Remove module_obj_name parameter from OBJECT_DECLARE* macros	2020-09-18 14:12:32 -04:00
disas	disas: Push const down through host disassembly	2021-01-07 05:09:42 -10:00
exec	memory: add readonly support to memory_region_init_ram_from_file()	2021-02-01 17:07:34 -05:00
fpu	softfloat: Define comparison operations for bfloat16	2020-08-29 19:25:42 -07:00
hw	hw/ssi: imx_spi: Use a macro for number of chip selects supported	2021-02-02 17:00:54 +00:00
io	io: Document qmp oob suitability of qio_channel_shutdown and io_shutdown	2021-01-13 10:21:17 +01:00
libdecnumber	include: Make headers more self-contained	2019-08-16 13:31:51 +02:00
migration	migration: Replace migration's JSON writer by the general one	2020-12-19 10:39:16 +01:00
monitor	sev: add sev-inject-launch-secret	2020-12-10 17:33:17 -05:00
net	net: checksum: Introduce fine control over checksum type	2021-01-25 17:04:56 +08:00
qapi	qapi: Introduce QAPI_LIST_APPEND	2021-01-28 08:08:45 +01:00
qemu	Machine queue, 2021-02-02	2021-02-03 09:54:21 +00:00
qom	qom: Add user_creatable_print_help_from_qdict()	2020-10-15 16:06:27 +02:00
scsi	scsi/utils: Add INVALID_PARAM_VALUE sense code definition	2021-01-22 14:51:35 +01:00
standard-headers	Update linux headers to 5.11-rc2	2021-01-21 11:19:45 +01:00
sysemu	block: Separate blk_is_writable() and blk_supports_write_perm()	2021-01-27 20:45:20 +01:00
tcg	tcg: Restart code generation when we run out of temps	2021-01-24 08:03:27 -10:00
ui	vnc: support "-vnc help"	2021-01-23 15:55:07 -05:00
user	trace: switch position of headers to what Meson requires	2020-08-21 06:18:24 -04:00
elf.h	target-arm queue:	2020-10-29 11:40:04 +00:00
glib-compat.h	glib-compat: add g_unix_get_passwd_entry_qemu()	2020-11-02 19:52:08 -06:00
qemu-common.h	vl: extract softmmu/datadir.c	2020-12-10 12:15:18 -05:00
qemu-io.h	Include qemu-common.h exactly where needed	2019-06-12 13:20:20 +02:00
trace-tcg.h