Xuzhou Cheng d6bafaf45c hw/ssi: xilinx_spips: Remove DMA related dead codes from zynqmp_spips ... Now that the Xilinx CSU DMA model is implemented, the existing DMA related dead codes in the ZynqMP QSPI are useless and should be removed. The maximum register number is also updated to only include the QSPI registers. Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com> Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20210303135254.3970-6-bmeng.cn@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>		2021-03-10 13:54:51 +00:00
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aspeed_smc.h	hw/ssi/aspeed_smc: Rename 'max_slaves' variable as 'max_peripherals'	2020-12-10 12:15:03 -05:00
imx_spi.h	hw/ssi: imx_spi: Use a macro for number of chip selects supported	2021-02-02 17:00:54 +00:00
mss-spi.h	Use OBJECT_DECLARE_SIMPLE_TYPE when possible	2020-09-18 14:12:32 -04:00
npcm7xx_fiu.h
pl022.h	arm: Update infocenter.arm.com URLs	2021-02-11 11:50:14 +00:00
sifive_spi.h	hw/ssi: Add SiFive SPI controller support	2021-03-04 09:43:29 -05:00
ssi.h	hw/ssi: Rename SSI 'slave' as 'peripheral'	2020-12-10 12:15:03 -05:00
stm32f2xx_spi.h	Use OBJECT_DECLARE_SIMPLE_TYPE when possible	2020-09-18 14:12:32 -04:00
xilinx_spips.h	hw/ssi: xilinx_spips: Remove DMA related dead codes from zynqmp_spips	2021-03-10 13:54:51 +00:00