Mateja Marjanovic 37b9aae2e6 target/mips: Preparing for adding MMI instructions ... Set up MMI code to be compiled only for TARGET_MIPS64. This is needed so that GPRs are 64 bit, and combined with MMI registers, they will form full 128 bit registers. Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1551183797-13570-2-git-send-email-mateja.marjanovic@rt-rk.com>		2019-02-27 14:26:14 +01:00
..
cp0_timer.c
cpu-qom.h
cpu.c	target/mips: Add disassembler support for nanoMIPS	2018-10-25 22:13:33 +02:00
cpu.h	target/mips: introduce MTTCG-enabled builds	2019-02-14 17:47:28 +01:00
dsp_helper.c
gdbstub.c
helper.c	target/mips: implement QMP query-cpu-definitions command	2019-02-21 19:36:47 +01:00
helper.h	target/mips: reimplement SC instruction emulation and use cmpxchg	2019-02-14 17:47:28 +01:00
internal.h	target/mips: Provide R/W access to SAARI and SAAR CP0 registers	2019-01-18 16:53:28 +01:00
kvm_mips.h
kvm.c
lmi_helper.c
machine.c	target/mips: compare virtual addresses in LL/SC sequence	2019-02-14 17:47:28 +01:00
Makefile.objs
mips-defs.h	target/mips: Define a bit for MXU in insn_flags	2018-10-29 14:13:47 +01:00
mips-semi.c
msa_helper.c
op_helper.c	target/mips: hold BQL in mips_vpe_wake()	2019-02-14 17:47:28 +01:00
TODO
trace-events
translate_init.inc.c	target/mips: Add I6500 core configuration	2019-01-24 17:48:33 +01:00
translate.c	target/mips: Preparing for adding MMI instructions	2019-02-27 14:26:14 +01:00