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98f96050aa
qemu/target/arm
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Richard Henderson 98f96050aa target/arm: Fix mte_checkN 
We were incorrectly assuming that only the first byte of an MTE access
is checked against the tags.  But per the ARM, unaligned accesses are
pre-decomposed into single-byte accesses.  So by the time we reach the
actual MTE check in the ARM pseudocode, all accesses are aligned.

Therefore, the first failure is always either the first byte of the
access, or the first byte of the granule.

In addition, some of the arithmetic is off for last-first -> count.
This does not become directly visible until a later patch that passes
single bytes into this function, so ptr == ptr_last.

Buglink: https://bugs.launchpad.net/bugs/1921948
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210416183106.1516563-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: tweaked a comment]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-04-30 11:16:49 +01:00
..
a32-uncond.decode arm tcg cpus: Fix Lesser GPL version number 2020-11-15 16:42:14 +01:00
a32.decode arm tcg cpus: Fix Lesser GPL version number 2020-11-15 16:42:14 +01:00
arch_dump.c target/arm: add spaces around operator 2020-11-10 11:03:47 +00:00
arm_ldst.h arm tcg cpus: Fix Lesser GPL version number 2020-11-15 16:42:14 +01:00
arm-powerctl.c arm/arm-powerctl: rebuild hflags after setting CP15 bits in arm_set_cpu_on() 2019-12-20 14:03:00 +00:00
arm-powerctl.h target/arm/arm-powerctl: Add new arm_set_cpu_on_and_reset() 2019-02-28 11:03:04 +00:00
cpu64.c Revert "target/arm: Make number of counters in PMCR follow the CPU" 2021-04-06 11:49:14 +01:00
cpu_tcg.c Revert "target/arm: Make number of counters in PMCR follow the CPU" 2021-04-06 11:49:14 +01:00
cpu-param.h linux-user/aarch64: Implement PR_TAGGED_ADDR_ENABLE 2021-02-16 13:06:16 +00:00
cpu-qom.h qom: Remove module_obj_name parameter from OBJECT_DECLARE* macros 2020-09-18 14:12:32 -04:00
cpu.c target/arm: Make M-profile VTOR loads on reset handle memory aliasing 2021-03-23 11:47:31 +00:00
cpu.h Revert "target/arm: Make number of counters in PMCR follow the CPU" 2021-04-06 11:49:14 +01:00
crypto_helper.c arm tcg cpus: Fix Lesser GPL version number 2020-11-15 16:42:14 +01:00
debug_helper.c target/arm: Stop assuming DBGDIDR always exists 2020-02-21 16:07:01 +00:00
gdbstub64.c arm tcg cpus: Fix Lesser GPL version number 2020-11-15 16:42:14 +01:00
gdbstub.c target/arm: use official org.gnu.gdb.aarch64.sve layout for registers 2021-01-18 10:05:06 +00:00
helper-a64.c target/arm: Speed up aarch64 TBL/TBX 2021-03-05 15:17:34 +00:00
helper-a64.h target/arm: Speed up aarch64 TBL/TBX 2021-03-05 15:17:34 +00:00
helper-sve.h arm tcg cpus: Fix Lesser GPL version number 2020-11-15 16:42:14 +01:00
helper.c Revert "target/arm: Make number of counters in PMCR follow the CPU" 2021-04-06 11:49:14 +01:00
helper.h target/arm: Fix neon VTBL/VTBX for len > 1 2020-11-10 11:03:48 +00:00
idau.h Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
internals.h target/arm: Add support for FEAT_SSBS, Speculative Store Bypass Safe 2021-03-05 15:17:34 +00:00
iwmmxt_helper.c arm tcg cpus: Fix Lesser GPL version number 2020-11-15 16:42:14 +01:00
kvm64.c Revert "target/arm: Make number of counters in PMCR follow the CPU" 2021-04-06 11:49:14 +01:00
kvm_arm.h hw/arm/virt: KVM: The IPA lower bound is 32 2021-03-12 12:47:11 +00:00
kvm-consts.h target/arm: Remove no-longer-reachable 32-bit KVM code 2020-09-14 14:23:19 +01:00
kvm-stub.c Include qemu-common.h exactly where needed 2019-06-12 13:20:20 +02:00
kvm.c hw/arm/virt: KVM: The IPA lower bound is 32 2021-03-12 12:47:11 +00:00
m_helper.c semihosting: Move include/hw/semihosting/ -> include/semihosting/ 2021-03-10 15:34:12 +00:00
m-nocp.decode target/arm: Implement new v8.1M VLLDM and VLSTM encodings 2020-12-10 11:44:56 +00:00
machine.c target/arm: Don't migrate CPUARMState.features 2021-02-11 11:50:13 +00:00
meson.build semihosting: Move ARM semihosting code to shared directories 2021-01-18 10:05:06 +00:00
monitor.c target/arm: Add cpu properties to control pauth 2021-01-19 14:38:51 +00:00
mte_helper.c target/arm: Fix mte_checkN 2021-04-30 11:16:49 +01:00
neon_helper.c target/arm: Convert Neon VADD, VSUB, VABD 3-reg-same insns to decodetree 2020-05-14 15:03:09 +01:00
neon-dp.decode arm tcg cpus: Fix Lesser GPL version number 2020-11-15 16:42:14 +01:00
neon-ls.decode arm tcg cpus: Fix Lesser GPL version number 2020-11-15 16:42:14 +01:00
neon-shared.decode arm tcg cpus: Fix Lesser GPL version number 2020-11-15 16:42:14 +01:00
op_addsub.h
op_helper.c target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate 2021-02-11 11:50:14 +00:00
pauth_helper.c target/arm: Implement an IMPDEF pauth algorithm 2021-01-19 14:38:51 +00:00
psci.c sysemu: Split sysemu/runstate.h off sysemu/sysemu.h 2019-08-16 13:37:36 +02:00
sve_helper.c target/arm: Update sve reduction vs simd_desc 2021-03-12 12:40:10 +00:00
sve.decode arm tcg cpus: Fix Lesser GPL version number 2020-11-15 16:42:14 +01:00
syndrome.h target/arm: Split out syndrome.h from internals.h 2021-02-16 13:16:18 +00:00
t16.decode arm tcg cpus: Fix Lesser GPL version number 2020-11-15 16:42:14 +01:00
t32.decode target/arm: Implement M-profile "minimal RAS implementation" 2020-12-10 11:44:56 +00:00
tlb_helper.c target/arm: Set ARMMMUFaultInfo.level in user-only arm_cpu_tlb_fill 2021-03-23 14:07:55 +00:00
trace-events trace-events: Shorten file names in comments 2019-03-22 16:18:07 +00:00
trace.h trace: switch position of headers to what Meson requires 2020-08-21 06:18:24 -04:00
translate-a64.c semihosting: Move include/hw/semihosting/ -> include/semihosting/ 2021-03-10 15:34:12 +00:00
translate-a64.h arm tcg cpus: Fix Lesser GPL version number 2020-11-15 16:42:14 +01:00
translate-neon.c.inc arm tcg cpus: Fix Lesser GPL version number 2020-11-15 16:42:14 +01:00
translate-sve.c target/arm: Update sve reduction vs simd_desc 2021-03-12 12:40:10 +00:00
translate-vfp.c.inc target/arm: Implement FPCXT_NS fp system register 2021-01-08 15:13:38 +00:00
translate.c target/arm: Make Thumb store insns UNDEF for Rn==1111 2021-04-30 11:16:49 +01:00
translate.h target/arm: Rearrange {sve,fp}_check_access assert 2020-08-28 10:02:47 +01:00
vec_helper.c target/arm: Speed up aarch64 TBL/TBX 2021-03-05 15:17:34 +00:00
vec_internal.h arm tcg cpus: Fix Lesser GPL version number 2020-11-15 16:42:14 +01:00
vfp_helper.c target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension 2020-10-20 16:12:01 +01:00
vfp-uncond.decode arm tcg cpus: Fix Lesser GPL version number 2020-11-15 16:42:14 +01:00
vfp.decode target/arm: Implement VLDR/VSTR system register 2020-12-10 11:44:55 +00:00