b07cd3e748
Here's a last minue pull request before today's soft freeze. Ideally I would have sent this earlier, but I was waiting for a couple of extra fixes I knew were close. And the freeze crept up on me, like always. Most of the changes here are bugfixes in any case. There are some cleanups as well, which have been in my staging tree for a little while. There are a couple of truly new features (some extensions to the sam460ex platform), but these are low risk, since they only affect a new and not really stabilized machine type anyway. Higlights are: * Mac platform improvements from Mark Cave-Ayland * Sam460ex improvements from BALATON Zoltan et al. * XICS interrupt handler cleanups from Cédric Le Goater * TCG improvements for atomic loads and stores from Richard Henderson * Assorted other bugfixes -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEdfRlhq5hpmzETofcbDjKyiDZs5IFAls7D8oACgkQbDjKyiDZ s5Lxmg//YzPfC/nKqTTKkyJPzh/NnSC+kRTMAT3mbxdRIc7yfgMqJtWGGbS1iKgK EeJ9hl5Qm0HfscfDuzf0xasU62ZEv3kNdLnWJEIgkqiXrxoO5KCnC0y4D8NN1W03 mvINNCa8+QDg2OsirGmNUTkriiG3wLIrHTpLZ4+JuC2Bd9H3nTHZgJ0MXON/1VWY oRgr6kMZ5+IAzPhvYLFR6l3nPI883fgJOFyRo7YqYrkVBKFrFkfK0Xjw6vpsNxcx 2dE/YCHhNIriLuBG5noewL7GuqZRtLnl6rjjee5VAKIe1EmFeR+jsXwNjzGOVOJg dhjOtsJsQQ3WdEw5uImJzE64kV228WCgmkeXzZd1010JBLr7sUkrd2EuoZ23vvat uvZAHVSBrJg5WvzMo1VMEoPU3VeeZQ5HL+MI80iKiU6oUgRK11gVJcebtA0sEKt+ zhJC4JiUlHtZLTGIpMBmU8DJZ3Tyk1cBEm+Ky+SaPE+dsz16UHI0fazFQXJnXphE MLHEGAyQgzWYp7kIcAjUFev0Geq/Uovy4JKIGI6ISop1wRPEQDxkthfkfRyQxQkE zuse4EBcEH/Undw9KrmEQa0hCe+8BRkxklVbPesFPPdqH3PKNxtHYuWpSShQF0PW XMjw43O2Rbsl8kBUHCpy4pYSugD1hpfgaw/mVUOU1u/M1O6toTw= =AHrx -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-3.0-20180703' into staging ppc patch queue 2018-07-03 Here's a last minue pull request before today's soft freeze. Ideally I would have sent this earlier, but I was waiting for a couple of extra fixes I knew were close. And the freeze crept up on me, like always. Most of the changes here are bugfixes in any case. There are some cleanups as well, which have been in my staging tree for a little while. There are a couple of truly new features (some extensions to the sam460ex platform), but these are low risk, since they only affect a new and not really stabilized machine type anyway. Higlights are: * Mac platform improvements from Mark Cave-Ayland * Sam460ex improvements from BALATON Zoltan et al. * XICS interrupt handler cleanups from Cédric Le Goater * TCG improvements for atomic loads and stores from Richard Henderson * Assorted other bugfixes # gpg: Signature made Tue 03 Jul 2018 06:55:22 BST # gpg: using RSA key 6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-3.0-20180703: (35 commits) ppc: Include vga cirrus card into the compiling process target/ppc: Relax reserved bitmask of indexed store instructions target/ppc: set is_jmp on ppc_tr_breakpoint_check spapr: compute default value of "hpt-max-page-size" later target/ppc/kvm: don't pass cpu to kvm_get_smmu_info() target/ppc/kvm: get rid of kvm_get_fallback_smmu_info() ppc440_uc: Basic emulation of PPC440 DMA controller sam460ex: Add RTC device hw/timer: Add basic M41T80 emulation ppc4xx_i2c: Rewrite to model hardware more closely hw/ppc: Give sam46ex its own config option fpu_helper.c: fix setting FPSCR[FI] bit target/ppc: Implement the rest of gen_st_atomic target/ppc: Implement the rest of gen_ld_atomic target/ppc: Use atomic min/max helpers target/ppc: Use MO_ALIGN for EXIWX and ECOWX target/ppc: Split out gen_st_atomic target/ppc: Split out gen_ld_atomic target/ppc: Split out gen_load_locked target/ppc: Tidy gen_conditional_store ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # hw/ppc/spapr.c
636 lines
20 KiB
C
636 lines
20 KiB
C
/*
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* QEMU aCube Sam460ex board emulation
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*
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* Copyright (c) 2012 François Revol
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* Copyright (c) 2016-2018 BALATON Zoltan
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*
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* This file is derived from hw/ppc440_bamboo.c,
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* the copyright for that material belongs to the original owners.
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*
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* This work is licensed under the GNU GPL license version 2 or later.
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*
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "qemu-common.h"
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#include "qemu/error-report.h"
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#include "qapi/error.h"
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#include "hw/hw.h"
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#include "hw/boards.h"
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#include "sysemu/kvm.h"
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#include "kvm_ppc.h"
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#include "sysemu/device_tree.h"
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#include "sysemu/block-backend.h"
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#include "hw/loader.h"
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#include "elf.h"
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#include "exec/address-spaces.h"
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#include "exec/memory.h"
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#include "ppc440.h"
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#include "ppc405.h"
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#include "hw/block/flash.h"
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#include "sysemu/sysemu.h"
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#include "sysemu/qtest.h"
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#include "hw/sysbus.h"
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#include "hw/char/serial.h"
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#include "hw/i2c/ppc4xx_i2c.h"
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#include "hw/i2c/smbus.h"
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#include "hw/usb/hcd-ehci.h"
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#include <libfdt.h>
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#define BINARY_DEVICE_TREE_FILE "canyonlands.dtb"
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#define UBOOT_FILENAME "u-boot-sam460-20100605.bin"
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/* to extract the official U-Boot bin from the updater: */
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/* dd bs=1 skip=$(($(stat -c '%s' updater/updater-460) - 0x80000)) \
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if=updater/updater-460 of=u-boot-sam460-20100605.bin */
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/* from Sam460 U-Boot include/configs/Sam460ex.h */
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#define FLASH_BASE 0xfff00000
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#define FLASH_BASE_H 0x4
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#define FLASH_SIZE (1 * MiB)
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#define UBOOT_LOAD_BASE 0xfff80000
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#define UBOOT_SIZE 0x00080000
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#define UBOOT_ENTRY 0xfffffffc
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/* from U-Boot */
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#define EPAPR_MAGIC (0x45504150)
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#define KERNEL_ADDR 0x1000000
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#define FDT_ADDR 0x1800000
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#define RAMDISK_ADDR 0x1900000
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/* Sam460ex IRQ MAP:
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IRQ0 = ETH_INT
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IRQ1 = FPGA_INT
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IRQ2 = PCI_INT (PCIA, PCIB, PCIC, PCIB)
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IRQ3 = FPGA_INT2
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IRQ11 = RTC_INT
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IRQ12 = SM502_INT
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*/
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#define CPU_FREQ 1150000000
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#define PLB_FREQ 230000000
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#define OPB_FREQ 115000000
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#define EBC_FREQ 115000000
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#define UART_FREQ 11059200
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#define SDRAM_NR_BANKS 4
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/* FIXME: See u-boot.git 8ac41e, also fix in ppc440_uc.c */
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static const unsigned int ppc460ex_sdram_bank_sizes[] = {
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1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 0
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};
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struct boot_info {
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uint32_t dt_base;
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uint32_t dt_size;
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uint32_t entry;
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};
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/*****************************************************************************/
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/* SPD eeprom content from mips_malta.c */
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struct _eeprom24c0x_t {
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uint8_t tick;
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uint8_t address;
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uint8_t command;
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uint8_t ack;
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uint8_t scl;
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uint8_t sda;
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uint8_t data;
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uint8_t contents[256];
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};
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typedef struct _eeprom24c0x_t eeprom24c0x_t;
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static eeprom24c0x_t spd_eeprom = {
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.contents = {
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/* 00000000: */ 0x80, 0x08, 0xFF, 0x0D, 0x0A, 0xFF, 0x40, 0x00,
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/* 00000008: */ 0x04, 0x75, 0x54, 0x00, 0x82, 0x08, 0x00, 0x01,
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/* 00000010: */ 0x8F, 0x04, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00,
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/* 00000018: */ 0x00, 0x00, 0x00, 0x14, 0x0F, 0x14, 0x2D, 0xFF,
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/* 00000020: */ 0x15, 0x08, 0x15, 0x08, 0x00, 0x00, 0x00, 0x00,
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/* 00000028: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 00000030: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 00000038: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0xD0,
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/* 00000040: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 00000048: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 00000050: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 00000058: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 00000060: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 00000068: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 00000070: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 00000078: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x64, 0xF4,
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},
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};
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static void generate_eeprom_spd(uint8_t *eeprom, ram_addr_t ram_size)
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{
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enum { SDR = 0x4, DDR1 = 0x7, DDR2 = 0x8 } type;
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uint8_t *spd = spd_eeprom.contents;
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uint8_t nbanks = 0;
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uint16_t density = 0;
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int i;
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/* work in terms of MB */
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ram_size /= MiB;
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while ((ram_size >= 4) && (nbanks <= 2)) {
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int sz_log2 = MIN(31 - clz32(ram_size), 14);
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nbanks++;
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density |= 1 << (sz_log2 - 2);
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ram_size -= 1 << sz_log2;
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}
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/* split to 2 banks if possible */
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if ((nbanks == 1) && (density > 1)) {
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nbanks++;
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density >>= 1;
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}
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if (density & 0xff00) {
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density = (density & 0xe0) | ((density >> 8) & 0x1f);
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type = DDR2;
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} else if (!(density & 0x1f)) {
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type = DDR2;
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} else {
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type = SDR;
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}
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if (ram_size) {
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warn_report("SPD cannot represent final " RAM_ADDR_FMT "MB"
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" of SDRAM", ram_size);
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}
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/* fill in SPD memory information */
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spd[2] = type;
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spd[5] = nbanks;
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spd[31] = density;
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/* XXX: this is totally random */
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spd[9] = 0x10; /* CAS tcyc */
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spd[18] = 0x20; /* CAS bit */
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spd[23] = 0x10; /* CAS tcyc */
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spd[25] = 0x10; /* CAS tcyc */
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/* checksum */
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spd[63] = 0;
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for (i = 0; i < 63; i++) {
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spd[63] += spd[i];
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}
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/* copy for SMBUS */
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memcpy(eeprom, spd, sizeof(spd_eeprom.contents));
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}
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static void generate_eeprom_serial(uint8_t *eeprom)
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{
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int i, pos = 0;
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uint8_t mac[6] = { 0x00 };
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uint8_t sn[5] = { 0x01, 0x23, 0x45, 0x67, 0x89 };
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/* version */
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eeprom[pos++] = 0x01;
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/* count */
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eeprom[pos++] = 0x02;
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/* MAC address */
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eeprom[pos++] = 0x01; /* MAC */
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eeprom[pos++] = 0x06; /* length */
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memcpy(&eeprom[pos], mac, sizeof(mac));
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pos += sizeof(mac);
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/* serial number */
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eeprom[pos++] = 0x02; /* serial */
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eeprom[pos++] = 0x05; /* length */
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memcpy(&eeprom[pos], sn, sizeof(sn));
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pos += sizeof(sn);
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/* checksum */
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eeprom[pos] = 0;
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for (i = 0; i < pos; i++) {
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eeprom[pos] += eeprom[i];
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}
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}
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/*****************************************************************************/
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static int sam460ex_load_uboot(void)
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{
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DriveInfo *dinfo;
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BlockBackend *blk = NULL;
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hwaddr base = FLASH_BASE | ((hwaddr)FLASH_BASE_H << 32);
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long bios_size = FLASH_SIZE;
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int fl_sectors;
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dinfo = drive_get(IF_PFLASH, 0, 0);
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if (dinfo) {
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blk = blk_by_legacy_dinfo(dinfo);
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bios_size = blk_getlength(blk);
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}
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fl_sectors = (bios_size + 65535) >> 16;
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if (!pflash_cfi01_register(base, NULL, "sam460ex.flash", bios_size,
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blk, 64 * KiB, fl_sectors,
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1, 0x89, 0x18, 0x0000, 0x0, 1)) {
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error_report("qemu: Error registering flash memory.");
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/* XXX: return an error instead? */
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exit(1);
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}
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if (!blk) {
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/*error_report("No flash image given with the 'pflash' parameter,"
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" using default u-boot image");*/
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base = UBOOT_LOAD_BASE | ((hwaddr)FLASH_BASE_H << 32);
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rom_add_file_fixed(UBOOT_FILENAME, base, -1);
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}
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return 0;
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}
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static int sam460ex_load_device_tree(hwaddr addr,
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uint32_t ramsize,
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hwaddr initrd_base,
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hwaddr initrd_size,
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const char *kernel_cmdline)
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{
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int ret = -1;
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uint32_t mem_reg_property[] = { 0, 0, cpu_to_be32(ramsize) };
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char *filename;
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int fdt_size;
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void *fdt;
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uint32_t tb_freq = CPU_FREQ;
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uint32_t clock_freq = CPU_FREQ;
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int offset;
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filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
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if (!filename) {
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goto out;
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}
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fdt = load_device_tree(filename, &fdt_size);
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g_free(filename);
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if (fdt == NULL) {
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goto out;
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}
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/* Manipulate device tree in memory. */
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ret = qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property,
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sizeof(mem_reg_property));
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if (ret < 0) {
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error_report("couldn't set /memory/reg");
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}
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/* default FDT doesn't have a /chosen node... */
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qemu_fdt_add_subnode(fdt, "/chosen");
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ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
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initrd_base);
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if (ret < 0) {
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error_report("couldn't set /chosen/linux,initrd-start");
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}
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ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
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(initrd_base + initrd_size));
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if (ret < 0) {
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error_report("couldn't set /chosen/linux,initrd-end");
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}
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ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
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kernel_cmdline);
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if (ret < 0) {
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error_report("couldn't set /chosen/bootargs");
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}
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/* Copy data from the host device tree into the guest. Since the guest can
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* directly access the timebase without host involvement, we must expose
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* the correct frequencies. */
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if (kvm_enabled()) {
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tb_freq = kvmppc_get_tbfreq();
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clock_freq = kvmppc_get_clockfreq();
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}
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qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "clock-frequency",
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clock_freq);
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qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "timebase-frequency",
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tb_freq);
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/* Remove cpm node if it exists (it is not emulated) */
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offset = fdt_path_offset(fdt, "/cpm");
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if (offset >= 0) {
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fdt_nop_node(fdt, offset);
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}
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/* set serial port clocks */
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offset = fdt_node_offset_by_compatible(fdt, -1, "ns16550");
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while (offset >= 0) {
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fdt_setprop_cell(fdt, offset, "clock-frequency", UART_FREQ);
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offset = fdt_node_offset_by_compatible(fdt, offset, "ns16550");
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}
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/* some more clocks */
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qemu_fdt_setprop_cell(fdt, "/plb", "clock-frequency",
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PLB_FREQ);
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qemu_fdt_setprop_cell(fdt, "/plb/opb", "clock-frequency",
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OPB_FREQ);
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qemu_fdt_setprop_cell(fdt, "/plb/opb/ebc", "clock-frequency",
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EBC_FREQ);
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rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);
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g_free(fdt);
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ret = fdt_size;
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out:
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return ret;
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}
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/* Create reset TLB entries for BookE, mapping only the flash memory. */
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static void mmubooke_create_initial_mapping_uboot(CPUPPCState *env)
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{
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ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];
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/* on reset the flash is mapped by a shadow TLB,
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* but since we don't implement them we need to use
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* the same values U-Boot will use to avoid a fault.
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*/
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tlb->attr = 0;
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tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
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tlb->size = 0x10000000; /* up to 0xffffffff */
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tlb->EPN = 0xf0000000 & TARGET_PAGE_MASK;
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tlb->RPN = (0xf0000000 & TARGET_PAGE_MASK) | 0x4;
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tlb->PID = 0;
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}
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/* Create reset TLB entries for BookE, spanning the 32bit addr space. */
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static void mmubooke_create_initial_mapping(CPUPPCState *env,
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target_ulong va,
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hwaddr pa)
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{
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ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];
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tlb->attr = 0;
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|
tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
|
|
tlb->size = 1 << 31; /* up to 0x80000000 */
|
|
tlb->EPN = va & TARGET_PAGE_MASK;
|
|
tlb->RPN = pa & TARGET_PAGE_MASK;
|
|
tlb->PID = 0;
|
|
}
|
|
|
|
static void main_cpu_reset(void *opaque)
|
|
{
|
|
PowerPCCPU *cpu = opaque;
|
|
CPUPPCState *env = &cpu->env;
|
|
struct boot_info *bi = env->load_info;
|
|
|
|
cpu_reset(CPU(cpu));
|
|
|
|
/* either we have a kernel to boot or we jump to U-Boot */
|
|
if (bi->entry != UBOOT_ENTRY) {
|
|
env->gpr[1] = (16 * MiB) - 8;
|
|
env->gpr[3] = FDT_ADDR;
|
|
env->nip = bi->entry;
|
|
|
|
/* Create a mapping for the kernel. */
|
|
mmubooke_create_initial_mapping(env, 0, 0);
|
|
env->gpr[6] = tswap32(EPAPR_MAGIC);
|
|
env->gpr[7] = (16 * MiB) - 8; /* bi->ima_size; */
|
|
|
|
} else {
|
|
env->nip = UBOOT_ENTRY;
|
|
mmubooke_create_initial_mapping_uboot(env);
|
|
}
|
|
}
|
|
|
|
static void sam460ex_init(MachineState *machine)
|
|
{
|
|
MemoryRegion *address_space_mem = get_system_memory();
|
|
MemoryRegion *isa = g_new(MemoryRegion, 1);
|
|
MemoryRegion *ram_memories = g_new(MemoryRegion, SDRAM_NR_BANKS);
|
|
hwaddr ram_bases[SDRAM_NR_BANKS];
|
|
hwaddr ram_sizes[SDRAM_NR_BANKS];
|
|
MemoryRegion *l2cache_ram = g_new(MemoryRegion, 1);
|
|
qemu_irq *irqs, *uic[4];
|
|
PCIBus *pci_bus;
|
|
PowerPCCPU *cpu;
|
|
CPUPPCState *env;
|
|
PPC4xxI2CState *i2c[2];
|
|
hwaddr entry = UBOOT_ENTRY;
|
|
hwaddr loadaddr = 0;
|
|
target_long initrd_size = 0;
|
|
DeviceState *dev;
|
|
SysBusDevice *sbdev;
|
|
int success;
|
|
int i;
|
|
struct boot_info *boot_info;
|
|
const size_t smbus_eeprom_size = 8 * 256;
|
|
uint8_t *smbus_eeprom_buf = g_malloc0(smbus_eeprom_size);
|
|
|
|
cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
|
|
env = &cpu->env;
|
|
if (env->mmu_model != POWERPC_MMU_BOOKE) {
|
|
error_report("Only MMU model BookE is supported by this machine.");
|
|
exit(1);
|
|
}
|
|
|
|
#ifdef TARGET_PPCEMB
|
|
if (!qtest_enabled()) {
|
|
warn_report("qemu-system-ppcemb is deprecated, "
|
|
"please use qemu-system-ppc instead.");
|
|
}
|
|
#endif
|
|
|
|
qemu_register_reset(main_cpu_reset, cpu);
|
|
boot_info = g_malloc0(sizeof(*boot_info));
|
|
env->load_info = boot_info;
|
|
|
|
ppc_booke_timers_init(cpu, CPU_FREQ, 0);
|
|
ppc_dcr_init(env, NULL, NULL);
|
|
|
|
/* PLB arbitrer */
|
|
ppc4xx_plb_init(env);
|
|
|
|
/* interrupt controllers */
|
|
irqs = g_malloc0(sizeof(*irqs) * PPCUIC_OUTPUT_NB);
|
|
irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
|
|
irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
|
|
uic[0] = ppcuic_init(env, irqs, 0xc0, 0, 1);
|
|
uic[1] = ppcuic_init(env, &uic[0][30], 0xd0, 0, 1);
|
|
uic[2] = ppcuic_init(env, &uic[0][10], 0xe0, 0, 1);
|
|
uic[3] = ppcuic_init(env, &uic[0][16], 0xf0, 0, 1);
|
|
|
|
/* SDRAM controller */
|
|
memset(ram_bases, 0, sizeof(ram_bases));
|
|
memset(ram_sizes, 0, sizeof(ram_sizes));
|
|
/* put all RAM on first bank because board has one slot
|
|
* and firmware only checks that */
|
|
machine->ram_size = ppc4xx_sdram_adjust(machine->ram_size, 1,
|
|
ram_memories, ram_bases, ram_sizes,
|
|
ppc460ex_sdram_bank_sizes);
|
|
|
|
/* FIXME: does 460EX have ECC interrupts? */
|
|
ppc440_sdram_init(env, SDRAM_NR_BANKS, ram_memories,
|
|
ram_bases, ram_sizes, 1);
|
|
|
|
/* generate SPD EEPROM data */
|
|
for (i = 0; i < SDRAM_NR_BANKS; i++) {
|
|
generate_eeprom_spd(&smbus_eeprom_buf[i * 256], ram_sizes[i]);
|
|
}
|
|
generate_eeprom_serial(&smbus_eeprom_buf[4 * 256]);
|
|
generate_eeprom_serial(&smbus_eeprom_buf[6 * 256]);
|
|
|
|
/* IIC controllers */
|
|
dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600700, uic[0][2]);
|
|
i2c[0] = PPC4xx_I2C(dev);
|
|
object_property_set_bool(OBJECT(dev), true, "realized", NULL);
|
|
smbus_eeprom_init(i2c[0]->bus, 8, smbus_eeprom_buf, smbus_eeprom_size);
|
|
g_free(smbus_eeprom_buf);
|
|
i2c_create_slave(i2c[0]->bus, "m41t80", 0x68);
|
|
|
|
dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600800, uic[0][3]);
|
|
i2c[1] = PPC4xx_I2C(dev);
|
|
|
|
/* External bus controller */
|
|
ppc405_ebc_init(env);
|
|
|
|
/* CPR */
|
|
ppc4xx_cpr_init(env);
|
|
|
|
/* PLB to AHB bridge */
|
|
ppc4xx_ahb_init(env);
|
|
|
|
/* System DCRs */
|
|
ppc4xx_sdr_init(env);
|
|
|
|
/* MAL */
|
|
ppc4xx_mal_init(env, 4, 16, &uic[2][3]);
|
|
|
|
/* DMA */
|
|
ppc4xx_dma_init(env, 0x200);
|
|
|
|
/* 256K of L2 cache as memory */
|
|
ppc4xx_l2sram_init(env);
|
|
/* FIXME: remove this after fixing l2sram mapping in ppc440_uc.c? */
|
|
memory_region_init_ram(l2cache_ram, NULL, "ppc440.l2cache_ram", 256 * KiB,
|
|
&error_abort);
|
|
memory_region_add_subregion(address_space_mem, 0x400000000LL, l2cache_ram);
|
|
|
|
/* USB */
|
|
sysbus_create_simple(TYPE_PPC4xx_EHCI, 0x4bffd0400, uic[2][29]);
|
|
dev = qdev_create(NULL, "sysbus-ohci");
|
|
qdev_prop_set_string(dev, "masterbus", "usb-bus.0");
|
|
qdev_prop_set_uint32(dev, "num-ports", 6);
|
|
qdev_init_nofail(dev);
|
|
sbdev = SYS_BUS_DEVICE(dev);
|
|
sysbus_mmio_map(sbdev, 0, 0x4bffd0000);
|
|
sysbus_connect_irq(sbdev, 0, uic[2][30]);
|
|
usb_create_simple(usb_bus_find(-1), "usb-kbd");
|
|
usb_create_simple(usb_bus_find(-1), "usb-mouse");
|
|
|
|
/* PCI bus */
|
|
ppc460ex_pcie_init(env);
|
|
/* FIXME: is this correct? */
|
|
dev = sysbus_create_varargs("ppc440-pcix-host", 0xc0ec00000,
|
|
uic[1][0], uic[1][20], uic[1][21], uic[1][22],
|
|
NULL);
|
|
pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
|
|
if (!pci_bus) {
|
|
error_report("couldn't create PCI controller!");
|
|
exit(1);
|
|
}
|
|
memory_region_init_alias(isa, NULL, "isa_mmio", get_system_io(),
|
|
0, 0x10000);
|
|
memory_region_add_subregion(get_system_memory(), 0xc08000000, isa);
|
|
|
|
/* PCI devices */
|
|
pci_create_simple(pci_bus, PCI_DEVFN(6, 0), "sm501");
|
|
/* SoC has a single SATA port but we don't emulate that yet
|
|
* However, firmware and usual clients have driver for SiI311x
|
|
* so add one for convenience by default */
|
|
if (defaults_enabled()) {
|
|
pci_create_simple(pci_bus, -1, "sii3112");
|
|
}
|
|
|
|
/* SoC has 4 UARTs
|
|
* but board has only one wired and two are present in fdt */
|
|
if (serial_hd(0) != NULL) {
|
|
serial_mm_init(address_space_mem, 0x4ef600300, 0, uic[1][1],
|
|
PPC_SERIAL_MM_BAUDBASE, serial_hd(0),
|
|
DEVICE_BIG_ENDIAN);
|
|
}
|
|
if (serial_hd(1) != NULL) {
|
|
serial_mm_init(address_space_mem, 0x4ef600400, 0, uic[0][1],
|
|
PPC_SERIAL_MM_BAUDBASE, serial_hd(1),
|
|
DEVICE_BIG_ENDIAN);
|
|
}
|
|
|
|
/* Load U-Boot image. */
|
|
if (!machine->kernel_filename) {
|
|
success = sam460ex_load_uboot();
|
|
if (success < 0) {
|
|
error_report("qemu: could not load firmware");
|
|
exit(1);
|
|
}
|
|
}
|
|
|
|
/* Load kernel. */
|
|
if (machine->kernel_filename) {
|
|
success = load_uimage(machine->kernel_filename, &entry, &loadaddr,
|
|
NULL, NULL, NULL);
|
|
if (success < 0) {
|
|
uint64_t elf_entry, elf_lowaddr;
|
|
|
|
success = load_elf(machine->kernel_filename, NULL, NULL, &elf_entry,
|
|
&elf_lowaddr, NULL, 1, PPC_ELF_MACHINE, 0, 0);
|
|
entry = elf_entry;
|
|
loadaddr = elf_lowaddr;
|
|
}
|
|
/* XXX try again as binary */
|
|
if (success < 0) {
|
|
error_report("qemu: could not load kernel '%s'",
|
|
machine->kernel_filename);
|
|
exit(1);
|
|
}
|
|
}
|
|
|
|
/* Load initrd. */
|
|
if (machine->initrd_filename) {
|
|
initrd_size = load_image_targphys(machine->initrd_filename,
|
|
RAMDISK_ADDR,
|
|
machine->ram_size - RAMDISK_ADDR);
|
|
if (initrd_size < 0) {
|
|
error_report("qemu: could not load ram disk '%s' at %x",
|
|
machine->initrd_filename, RAMDISK_ADDR);
|
|
exit(1);
|
|
}
|
|
}
|
|
|
|
/* If we're loading a kernel directly, we must load the device tree too. */
|
|
if (machine->kernel_filename) {
|
|
int dt_size;
|
|
|
|
dt_size = sam460ex_load_device_tree(FDT_ADDR, machine->ram_size,
|
|
RAMDISK_ADDR, initrd_size,
|
|
machine->kernel_cmdline);
|
|
if (dt_size < 0) {
|
|
error_report("couldn't load device tree");
|
|
exit(1);
|
|
}
|
|
|
|
boot_info->dt_base = FDT_ADDR;
|
|
boot_info->dt_size = dt_size;
|
|
}
|
|
|
|
boot_info->entry = entry;
|
|
}
|
|
|
|
static void sam460ex_machine_init(MachineClass *mc)
|
|
{
|
|
mc->desc = "aCube Sam460ex";
|
|
mc->init = sam460ex_init;
|
|
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("460exb");
|
|
mc->default_ram_size = 512 * MiB;
|
|
}
|
|
|
|
DEFINE_MACHINE("sam460ex", sam460ex_machine_init)
|