c6d8ed24b4
Supports CONFIG_QEMU_LDST_OPTIMIZATION Signed-off-by: Jani Kokkonen <jani.kokkonen@huawei.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
454 lines
15 KiB
C
454 lines
15 KiB
C
/*
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* internal execution defines for qemu
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _EXEC_ALL_H_
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#define _EXEC_ALL_H_
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#include "qemu-common.h"
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/* allow to see translation results - the slowdown should be negligible, so we leave it */
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#define DEBUG_DISAS
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/* Page tracking code uses ram addresses in system mode, and virtual
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addresses in userspace mode. Define tb_page_addr_t to be an appropriate
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type. */
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#if defined(CONFIG_USER_ONLY)
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typedef abi_ulong tb_page_addr_t;
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#else
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typedef ram_addr_t tb_page_addr_t;
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#endif
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/* is_jmp field values */
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#define DISAS_NEXT 0 /* next instruction can be analyzed */
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#define DISAS_JUMP 1 /* only pc was modified dynamically */
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#define DISAS_UPDATE 2 /* cpu state was modified dynamically */
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#define DISAS_TB_JUMP 3 /* only pc was modified statically */
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struct TranslationBlock;
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typedef struct TranslationBlock TranslationBlock;
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/* XXX: make safe guess about sizes */
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#define MAX_OP_PER_INSTR 208
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#if HOST_LONG_BITS == 32
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#define MAX_OPC_PARAM_PER_ARG 2
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#else
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#define MAX_OPC_PARAM_PER_ARG 1
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#endif
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#define MAX_OPC_PARAM_IARGS 5
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#define MAX_OPC_PARAM_OARGS 1
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#define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
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/* A Call op needs up to 4 + 2N parameters on 32-bit archs,
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* and up to 4 + N parameters on 64-bit archs
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* (N = number of input arguments + output arguments). */
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#define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
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#define OPC_BUF_SIZE 640
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#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
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/* Maximum size a TCG op can expand to. This is complicated because a
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single op may require several host instructions and register reloads.
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For now take a wild guess at 192 bytes, which should allow at least
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a couple of fixup instructions per argument. */
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#define TCG_MAX_OP_SIZE 192
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#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
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#include "qemu/log.h"
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void gen_intermediate_code(CPUArchState *env, struct TranslationBlock *tb);
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void gen_intermediate_code_pc(CPUArchState *env, struct TranslationBlock *tb);
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void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb,
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int pc_pos);
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void cpu_gen_init(void);
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int cpu_gen_code(CPUArchState *env, struct TranslationBlock *tb,
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int *gen_code_size_ptr);
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bool cpu_restore_state(CPUArchState *env, uintptr_t searched_pc);
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void QEMU_NORETURN cpu_resume_from_signal(CPUArchState *env1, void *puc);
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void QEMU_NORETURN cpu_io_recompile(CPUArchState *env, uintptr_t retaddr);
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TranslationBlock *tb_gen_code(CPUArchState *env,
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target_ulong pc, target_ulong cs_base, int flags,
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int cflags);
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void cpu_exec_init(CPUArchState *env);
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void QEMU_NORETURN cpu_loop_exit(CPUArchState *env1);
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int page_unprotect(target_ulong address, uintptr_t pc, void *puc);
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void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
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int is_cpu_write_access);
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void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end,
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int is_cpu_write_access);
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#if !defined(CONFIG_USER_ONLY)
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/* cputlb.c */
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void tlb_flush_page(CPUArchState *env, target_ulong addr);
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void tlb_flush(CPUArchState *env, int flush_global);
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void tlb_set_page(CPUArchState *env, target_ulong vaddr,
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hwaddr paddr, int prot,
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int mmu_idx, target_ulong size);
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void tb_invalidate_phys_addr(hwaddr addr);
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#else
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static inline void tlb_flush_page(CPUArchState *env, target_ulong addr)
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{
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}
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static inline void tlb_flush(CPUArchState *env, int flush_global)
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{
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}
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#endif
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#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
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#define CODE_GEN_PHYS_HASH_BITS 15
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#define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS)
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/* estimated block size for TB allocation */
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/* XXX: use a per code average code fragment size and modulate it
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according to the host CPU */
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#if defined(CONFIG_SOFTMMU)
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#define CODE_GEN_AVG_BLOCK_SIZE 128
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#else
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#define CODE_GEN_AVG_BLOCK_SIZE 64
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#endif
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#if defined(__arm__) || defined(_ARCH_PPC) \
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|| defined(__x86_64__) || defined(__i386__) \
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|| defined(__sparc__) || defined(__aarch64__) \
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|| defined(CONFIG_TCG_INTERPRETER)
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#define USE_DIRECT_JUMP
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#endif
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struct TranslationBlock {
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target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
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target_ulong cs_base; /* CS base for this block */
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uint64_t flags; /* flags defining in which context the code was generated */
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uint16_t size; /* size of target code for this block (1 <=
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size <= TARGET_PAGE_SIZE) */
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uint16_t cflags; /* compile flags */
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#define CF_COUNT_MASK 0x7fff
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#define CF_LAST_IO 0x8000 /* Last insn may be an IO access. */
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uint8_t *tc_ptr; /* pointer to the translated code */
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/* next matching tb for physical address. */
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struct TranslationBlock *phys_hash_next;
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/* first and second physical page containing code. The lower bit
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of the pointer tells the index in page_next[] */
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struct TranslationBlock *page_next[2];
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tb_page_addr_t page_addr[2];
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/* the following data are used to directly call another TB from
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the code of this one. */
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uint16_t tb_next_offset[2]; /* offset of original jump target */
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#ifdef USE_DIRECT_JUMP
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uint16_t tb_jmp_offset[2]; /* offset of jump instruction */
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#else
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uintptr_t tb_next[2]; /* address of jump generated code */
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#endif
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/* list of TBs jumping to this one. This is a circular list using
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the two least significant bits of the pointers to tell what is
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the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
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jmp_first */
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struct TranslationBlock *jmp_next[2];
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struct TranslationBlock *jmp_first;
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uint32_t icount;
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};
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#include "exec/spinlock.h"
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typedef struct TBContext TBContext;
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struct TBContext {
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TranslationBlock *tbs;
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TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
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int nb_tbs;
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/* any access to the tbs or the page table must use this lock */
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spinlock_t tb_lock;
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/* statistics */
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int tb_flush_count;
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int tb_phys_invalidate_count;
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int tb_invalidated_flag;
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};
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static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
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{
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target_ulong tmp;
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tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
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return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK;
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}
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static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
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{
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target_ulong tmp;
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tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
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return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
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| (tmp & TB_JMP_ADDR_MASK));
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}
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static inline unsigned int tb_phys_hash_func(tb_page_addr_t pc)
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{
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return (pc >> 2) & (CODE_GEN_PHYS_HASH_SIZE - 1);
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}
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void tb_free(TranslationBlock *tb);
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void tb_flush(CPUArchState *env);
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void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
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#if defined(USE_DIRECT_JUMP)
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#if defined(CONFIG_TCG_INTERPRETER)
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static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
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{
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/* patch the branch destination */
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*(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
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/* no need to flush icache explicitly */
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}
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#elif defined(_ARCH_PPC)
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void ppc_tb_set_jmp_target(unsigned long jmp_addr, unsigned long addr);
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#define tb_set_jmp_target1 ppc_tb_set_jmp_target
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#elif defined(__i386__) || defined(__x86_64__)
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static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
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{
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/* patch the branch destination */
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*(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
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/* no need to flush icache explicitly */
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}
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#elif defined(__aarch64__)
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void aarch64_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr);
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#define tb_set_jmp_target1 aarch64_tb_set_jmp_target
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#elif defined(__arm__)
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static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
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{
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#if !QEMU_GNUC_PREREQ(4, 1)
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register unsigned long _beg __asm ("a1");
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register unsigned long _end __asm ("a2");
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register unsigned long _flg __asm ("a3");
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#endif
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/* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
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*(uint32_t *)jmp_addr =
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(*(uint32_t *)jmp_addr & ~0xffffff)
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| (((addr - (jmp_addr + 8)) >> 2) & 0xffffff);
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#if QEMU_GNUC_PREREQ(4, 1)
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__builtin___clear_cache((char *) jmp_addr, (char *) jmp_addr + 4);
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#else
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/* flush icache */
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_beg = jmp_addr;
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_end = jmp_addr + 4;
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_flg = 0;
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__asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
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#endif
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}
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#elif defined(__sparc__)
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void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr);
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#else
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#error tb_set_jmp_target1 is missing
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#endif
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static inline void tb_set_jmp_target(TranslationBlock *tb,
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int n, uintptr_t addr)
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{
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uint16_t offset = tb->tb_jmp_offset[n];
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tb_set_jmp_target1((uintptr_t)(tb->tc_ptr + offset), addr);
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}
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#else
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/* set the jump target */
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static inline void tb_set_jmp_target(TranslationBlock *tb,
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int n, uintptr_t addr)
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{
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tb->tb_next[n] = addr;
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}
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#endif
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static inline void tb_add_jump(TranslationBlock *tb, int n,
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TranslationBlock *tb_next)
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{
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/* NOTE: this test is only needed for thread safety */
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if (!tb->jmp_next[n]) {
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/* patch the native jump address */
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tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc_ptr);
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/* add in TB jmp circular list */
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tb->jmp_next[n] = tb_next->jmp_first;
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tb_next->jmp_first = (TranslationBlock *)((uintptr_t)(tb) | (n));
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}
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}
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/* The return address may point to the start of the next instruction.
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Subtracting one gets us the call instruction itself. */
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#if defined(CONFIG_TCG_INTERPRETER)
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extern uintptr_t tci_tb_ptr;
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# define GETPC() tci_tb_ptr
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#elif defined(__s390__) && !defined(__s390x__)
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# define GETPC() \
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(((uintptr_t)__builtin_return_address(0) & 0x7fffffffUL) - 1)
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#elif defined(__arm__)
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/* Thumb return addresses have the low bit set, so we need to subtract two.
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This is still safe in ARM mode because instructions are 4 bytes. */
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# define GETPC() ((uintptr_t)__builtin_return_address(0) - 2)
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#else
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# define GETPC() ((uintptr_t)__builtin_return_address(0) - 1)
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#endif
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#if defined(CONFIG_QEMU_LDST_OPTIMIZATION) && defined(CONFIG_SOFTMMU)
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/* qemu_ld/st optimization split code generation to fast and slow path, thus,
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it needs special handling for an MMU helper which is called from the slow
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path, to get the fast path's pc without any additional argument.
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It uses a tricky solution which embeds the fast path pc into the slow path.
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Code flow in slow path:
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(1) pre-process
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(2) call MMU helper
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(3) jump to (5)
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(4) fast path information (implementation specific)
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(5) post-process (e.g. stack adjust)
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(6) jump to corresponding code of the next of fast path
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*/
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# if defined(__i386__) || defined(__x86_64__)
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/* To avoid broken disassembling, long jmp is used for embedding fast path pc,
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so that the destination is the next code of fast path, though this jmp is
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never executed.
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call MMU helper
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jmp POST_PROC (2byte) <- GETRA()
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jmp NEXT_CODE (5byte)
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POST_PROCESS ... <- GETRA() + 7
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*/
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# define GETRA() ((uintptr_t)__builtin_return_address(0))
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# define GETPC_LDST() ((uintptr_t)(GETRA() + 7 + \
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*(int32_t *)((void *)GETRA() + 3) - 1))
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# elif defined (_ARCH_PPC) && !defined (_ARCH_PPC64)
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# define GETRA() ((uintptr_t)__builtin_return_address(0))
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# define GETPC_LDST() ((uintptr_t) ((*(int32_t *)(GETRA() - 4)) - 1))
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# elif defined(__arm__)
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/* We define two insns between the return address and the branch back to
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straight-line. Find and decode that branch insn. */
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# define GETRA() ((uintptr_t)__builtin_return_address(0))
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# define GETPC_LDST() tcg_getpc_ldst(GETRA())
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static inline uintptr_t tcg_getpc_ldst(uintptr_t ra)
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{
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int32_t b;
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ra += 8; /* skip the two insns */
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b = *(int32_t *)ra; /* load the branch insn */
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b = (b << 8) >> (8 - 2); /* extract the displacement */
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ra += 8; /* branches are relative to pc+8 */
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ra += b; /* apply the displacement */
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ra -= 4; /* return a pointer into the current opcode,
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not the start of the next opcode */
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return ra;
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}
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#elif defined(__aarch64__)
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# define GETRA() ((uintptr_t)__builtin_return_address(0))
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# define GETPC_LDST() tcg_getpc_ldst(GETRA())
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static inline uintptr_t tcg_getpc_ldst(uintptr_t ra)
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{
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int32_t b;
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ra += 4; /* skip one instruction */
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b = *(int32_t *)ra; /* load the branch insn */
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b = (b << 6) >> (6 - 2); /* extract the displacement */
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ra += b; /* apply the displacement */
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ra -= 4; /* return a pointer into the current opcode,
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not the start of the next opcode */
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return ra;
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}
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# else
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# error "CONFIG_QEMU_LDST_OPTIMIZATION needs GETPC_LDST() implementation!"
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# endif
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bool is_tcg_gen_code(uintptr_t pc_ptr);
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# define GETPC_EXT() (is_tcg_gen_code(GETRA()) ? GETPC_LDST() : GETPC())
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#else
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# define GETPC_EXT() GETPC()
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#endif
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#if !defined(CONFIG_USER_ONLY)
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struct MemoryRegion *iotlb_to_region(hwaddr index);
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bool io_mem_read(struct MemoryRegion *mr, hwaddr addr,
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uint64_t *pvalue, unsigned size);
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bool io_mem_write(struct MemoryRegion *mr, hwaddr addr,
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uint64_t value, unsigned size);
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void tlb_fill(CPUArchState *env1, target_ulong addr, int is_write, int mmu_idx,
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uintptr_t retaddr);
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#include "exec/softmmu_defs.h"
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#define ACCESS_TYPE (NB_MMU_MODES + 1)
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#define MEMSUFFIX _code
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#define DATA_SIZE 1
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#include "exec/softmmu_header.h"
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#define DATA_SIZE 2
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#include "exec/softmmu_header.h"
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#define DATA_SIZE 4
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#include "exec/softmmu_header.h"
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#define DATA_SIZE 8
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#include "exec/softmmu_header.h"
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#undef ACCESS_TYPE
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#undef MEMSUFFIX
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#endif
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#if defined(CONFIG_USER_ONLY)
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static inline tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
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{
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return addr;
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}
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#else
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/* cputlb.c */
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tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr);
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#endif
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typedef void (CPUDebugExcpHandler)(CPUArchState *env);
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void cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler);
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/* vl.c */
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extern int singlestep;
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/* cpu-exec.c */
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extern volatile sig_atomic_t exit_request;
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/* Deterministic execution requires that IO only be performed on the last
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instruction of a TB so that interrupts take effect immediately. */
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static inline int can_do_io(CPUArchState *env)
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{
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CPUState *cpu = ENV_GET_CPU(env);
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if (!use_icount) {
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return 1;
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}
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/* If not executing code then assume we are ok. */
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if (cpu->current_tb == NULL) {
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return 1;
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}
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return env->can_do_io != 0;
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}
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#endif
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