f6ff4923b9
The microblaze architecture does not reorder instructions.
While there is an MBAR wait-for-data-access instruction,
this concerns synchronizing with DMA.
This should have been defined when enabling MTTCG.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com>
Fixes:
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.. | ||
cpu-param.h | ||
cpu-qom.h | ||
cpu.c | ||
cpu.h | ||
gdbstub.c | ||
helper.c | ||
helper.h | ||
insns.decode | ||
Kconfig | ||
machine.c | ||
meson.build | ||
mmu.c | ||
mmu.h | ||
op_helper.c | ||
translate.c |