97be8c6a95
Split host_signal_pc and host_signal_write out of user-exec.c. Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
86 lines
2.0 KiB
C
86 lines
2.0 KiB
C
/*
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* host-signal.h: signal info dependent on the host architecture
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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* Copyright (c) 2021 Linaro Limited
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*
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* This work is licensed under the terms of the GNU LGPL, version 2.1 or later.
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* See the COPYING file in the top-level directory.
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*/
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#ifndef RISCV_HOST_SIGNAL_H
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#define RISCV_HOST_SIGNAL_H
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static inline uintptr_t host_signal_pc(ucontext_t *uc)
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{
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return uc->uc_mcontext.__gregs[REG_PC];
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}
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static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc)
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{
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uint32_t insn = *(uint32_t *)host_signal_pc(uc);
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/*
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* Detect store by reading the instruction at the program
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* counter. Note: we currently only generate 32-bit
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* instructions so we thus only detect 32-bit stores
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*/
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switch (((insn >> 0) & 0b11)) {
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case 3:
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switch (((insn >> 2) & 0b11111)) {
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case 8:
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switch (((insn >> 12) & 0b111)) {
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case 0: /* sb */
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case 1: /* sh */
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case 2: /* sw */
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case 3: /* sd */
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case 4: /* sq */
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return true;
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default:
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break;
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}
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break;
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case 9:
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switch (((insn >> 12) & 0b111)) {
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case 2: /* fsw */
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case 3: /* fsd */
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case 4: /* fsq */
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return true;
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default:
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break;
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}
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break;
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default:
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break;
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}
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}
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/* Check for compressed instructions */
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switch (((insn >> 13) & 0b111)) {
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case 7:
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switch (insn & 0b11) {
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case 0: /*c.sd */
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case 2: /* c.sdsp */
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return true;
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default:
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break;
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}
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break;
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case 6:
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switch (insn & 0b11) {
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case 0: /* c.sw */
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case 3: /* c.swsp */
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return true;
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default:
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break;
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}
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break;
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default:
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break;
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}
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return false;
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}
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#endif
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