4ea5fe997d
These inline helpers are all used by target specific code so move them out of the general header so we don't needlessly pollute the rest of the API with target specific stuff. Note we have to include cpu.h in semihosting as it was relying on a side effect before. Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20230302190846.2593720-21-alex.bennee@linaro.org> Message-Id: <20230303025805.625589-21-richard.henderson@linaro.org>
89 lines
2.3 KiB
C
89 lines
2.3 KiB
C
/*
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* OpenRISC gdb server stub
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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* Copyright (c) 2013 SUSE LINUX Products GmbH
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "gdbstub/helpers.h"
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int openrisc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
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{
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OpenRISCCPU *cpu = OPENRISC_CPU(cs);
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CPUOpenRISCState *env = &cpu->env;
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if (n < 32) {
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return gdb_get_reg32(mem_buf, cpu_get_gpr(env, n));
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} else {
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switch (n) {
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case 32: /* PPC */
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return gdb_get_reg32(mem_buf, env->ppc);
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case 33: /* NPC (equals PC) */
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return gdb_get_reg32(mem_buf, env->pc);
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case 34: /* SR */
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return gdb_get_reg32(mem_buf, cpu_get_sr(env));
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default:
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break;
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}
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}
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return 0;
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}
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int openrisc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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{
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OpenRISCCPU *cpu = OPENRISC_CPU(cs);
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CPUClass *cc = CPU_GET_CLASS(cs);
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CPUOpenRISCState *env = &cpu->env;
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uint32_t tmp;
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if (n > cc->gdb_num_core_regs) {
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return 0;
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}
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tmp = ldl_p(mem_buf);
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if (n < 32) {
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cpu_set_gpr(env, n, tmp);
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} else {
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switch (n) {
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case 32: /* PPC */
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env->ppc = tmp;
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break;
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case 33: /* NPC (equals PC) */
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/* If setting PC to something different,
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also clear delayed branch status. */
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if (env->pc != tmp) {
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env->pc = tmp;
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env->dflag = 0;
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}
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break;
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case 34: /* SR */
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cpu_set_sr(env, tmp);
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break;
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default:
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break;
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}
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}
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return 4;
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}
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