0ca9fa2e3c
Add OpenRISC Multicore PIC which handles inter processor interrupts (IPI) between cores. In OpenRISC all device interrupts are routed to each core enabling this device to be simple. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
6 lines
96 B
Makefile
6 lines
96 B
Makefile
# Default configuration for or1k-softmmu
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CONFIG_SERIAL=y
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CONFIG_OPENCORES_ETH=y
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CONFIG_OMPIC=y
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