Bernhard Beschow 96c7fff703 hw/riscv/sifive_u: Resolve redundant property accessors ... The QOM API already provides accessors for uint32 values, so reuse them. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220301225220.239065-3-shentey@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2022-05-24 10:38:50 +10:00
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boot.c	hw/riscv: boot: Support 64bit fdt address.	2022-04-22 10:35:16 +10:00
Kconfig	hw/riscv: Enable TPM backends	2022-04-29 10:48:48 +10:00
meson.build	hw/riscv/Kconfig: Restrict NUMA to Virt & Spike machines	2021-07-20 15:32:49 +02:00
microchip_pfsoc.c	hw/riscv: Don't add empty bootargs to device tree	2022-04-29 10:47:45 +10:00
numa.c	hw: Do not include qemu/log.h if it is not necessary	2021-05-02 17:24:50 +02:00
opentitan.c	hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)	2022-05-24 10:38:50 +10:00
riscv_hart.c	hw/riscv: hart: Add a new 'resetvec' property	2020-09-09 15:54:18 -07:00
shakti_c.c	hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id	2021-10-22 23:35:47 +10:00
sifive_e.c	hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)	2022-05-24 10:38:50 +10:00
sifive_u.c	hw/riscv/sifive_u: Resolve redundant property accessors	2022-05-24 10:38:50 +10:00
spike.c	hw/riscv: Make CPU config error handling generous (virt/spike)	2022-05-24 10:38:50 +10:00
virt.c	hw/riscv: Make CPU config error handling generous (virt/spike)	2022-05-24 10:38:50 +10:00