qemu/target
Fredrik Noring 96631327be target/mips: Make R5900 DMULT[U], DDIV[U], LL[D] and SC[D] user only
The Linux kernel traps certain reserved instruction exceptions to
emulate the corresponding instructions. QEMU plays the role of the
kernel in user mode, so those traps are emulated by accepting the
instructions.

This change adds the function check_insn_opc_user_only to signal a
reserved instruction exception for flagged CPUs in QEMU system mode.

The MIPS III instructions DMULT[U], DDIV[U], LL[D] and SC[D] are not
implemented in R5900 hardware. They are trapped and emulated by the
Linux kernel and, accordingly, therefore QEMU user only instructions.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Fredrik Noring <noring@nocrew.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24 15:20:31 +02:00
..
alpha target/alpha: remove tlb_flush from alpha_cpu_initfn 2018-10-18 18:58:10 -07:00
arm target/arm: Check HAVE_CMPXCHG128 at translate time 2018-10-18 19:46:53 -07:00
cris target/cris/translate: Get rid of qemu_log_separate() 2018-10-16 17:57:23 +02:00
hppa target/hppa: Raise exception 26 on emulated hardware 2018-10-16 15:32:22 -07:00
i386 Error reporting patches for 2018-10-22 2018-10-23 17:20:23 +01:00
lm32 tcg-next queue 2018-06-04 11:28:31 +01:00
m68k target/m68k: Merge disas_m68k_insn into m68k_tr_translate_insn 2018-06-11 12:43:42 +02:00
microblaze target-microblaze: Rework NOP/zero instruction handling 2018-06-15 09:05:00 +02:00
mips target/mips: Make R5900 DMULT[U], DDIV[U], LL[D] and SC[D] user only 2018-10-24 15:20:31 +02:00
moxie tcg-next queue 2018-06-04 11:28:31 +01:00
nios2 tcg-next queue 2018-06-04 11:28:31 +01:00
openrisc target/openrisc: Fix writes to interrupt mask register 2018-07-03 22:40:33 +09:00
ppc Error reporting patches for 2018-10-22 2018-10-23 17:20:23 +01:00
riscv riscv: remove define cpu_init() 2018-09-05 09:58:38 -07:00
s390x target/s390x: Check HAVE_ATOMIC128 and HAVE_CMPXCHG128 at translate 2018-10-18 19:46:53 -07:00
sh4 sh4: fix use_icount with linux-user 2018-08-20 00:11:06 +02:00
sparc SPARC64: add icount support 2018-06-17 11:13:06 +01:00
tilegx tcg-next queue 2018-06-04 11:28:31 +01:00
tricore tcg: Pass tb and index to tcg_gen_exit_tb separately 2018-06-01 15:15:27 -07:00
unicore32 target/unicore32: remove tlb_flush from uc32_init_fn 2018-10-18 18:58:10 -07:00
xtensa target/xtensa: extract gen_check_interrupts call 2018-10-01 11:08:36 -07:00