qemu/target-ppc
Alexander Graf 41557447d3 PPC: Redesign interrupt trigger path
According to the Book3S spec, the interrupt context starts with an MSR
value that is rather simple. If we leave out the HV case, it's almost
always 0.

To reflect this, let's redesign the way that MSR value gets calculated.
Using this, we also squash the bug where MSR_POW can slip through into
the interrupt handler MSR.

Reported-by: Thomas Monjalon <thomas.monjalon@openwide.fr>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2010-09-15 16:18:33 +02:00
..
cpu.h remove exec-all.h inclusion from cpu.h 2010-07-03 09:48:24 +03:00
exec.h
helper_regs.h
helper.c PPC: Redesign interrupt trigger path 2010-09-15 16:18:33 +02:00
helper.h target-ppc: add vexptefp instruction 2010-07-13 18:18:32 +02:00
kvm_ppc.c
kvm_ppc.h KVM: PPC: Add level based interrupt logic 2010-09-05 11:50:48 +02:00
kvm.c KVM: PPC: Add level based interrupt logic 2010-09-05 11:50:48 +02:00
machine.c
mfrom_table_gen.c
mfrom_table.c
op_helper.c target-ppc: add vexptefp instruction 2010-07-13 18:18:32 +02:00
STATUS
translate_init.c target-ppc: fix power mode checking on 7400/7410 2010-07-19 00:33:29 +02:00
translate.c PPC: Enable hint bits for lwarx/ldarx 2010-09-15 16:18:27 +02:00