e3d0814368
Use device_class_set_legacy_reset() instead of opencoding an assignment to DeviceClass::reset. This change was produced with: spatch --macro-file scripts/cocci-macro-file.h \ --sp-file scripts/coccinelle/device-reset.cocci \ --keep-comments --smpl-spacing --in-place --dir hw Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240830145812.1967042-8-peter.maydell@linaro.org
572 lines
17 KiB
C
572 lines
17 KiB
C
/*
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* tpm_tis_i2c.c - QEMU's TPM TIS I2C Device
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*
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* Copyright (c) 2023 IBM Corporation
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*
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* Authors:
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* Ninad Palsule <ninad@linux.ibm.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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* TPM I2C implementation follows TCG TPM I2c Interface specification,
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* Family 2.0, Level 00, Revision 1.00
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*
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* TPM TIS for TPM 2 implementation following TCG PC Client Platform
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* TPM Profile (PTP) Specification, Family 2.0, Revision 00.43
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*
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*/
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#include "qemu/osdep.h"
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#include "hw/i2c/i2c.h"
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#include "hw/sysbus.h"
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#include "hw/acpi/tpm.h"
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#include "migration/vmstate.h"
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#include "tpm_prop.h"
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#include "qemu/log.h"
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#include "trace.h"
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#include "tpm_tis.h"
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/* Operations */
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#define OP_SEND 1
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#define OP_RECV 2
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/* Is locality valid */
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#define TPM_TIS_I2C_IS_VALID_LOCTY(x) TPM_TIS_IS_VALID_LOCTY(x)
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typedef struct TPMStateI2C {
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/*< private >*/
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I2CSlave parent_obj;
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uint8_t offset; /* offset into data[] */
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uint8_t operation; /* OP_SEND & OP_RECV */
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uint8_t data[5]; /* Data */
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/* i2c registers */
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uint8_t loc_sel; /* Current locality */
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uint8_t csum_enable; /* Is checksum enabled */
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/* Derived from the above */
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const char *reg_name; /* Register name */
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uint32_t tis_addr; /* Converted tis address including locty */
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/*< public >*/
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TPMState state; /* not a QOM object */
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} TPMStateI2C;
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DECLARE_INSTANCE_CHECKER(TPMStateI2C, TPM_TIS_I2C,
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TYPE_TPM_TIS_I2C)
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/* Prototype */
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static inline void tpm_tis_i2c_to_tis_reg(TPMStateI2C *i2cst, uint8_t i2c_reg);
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/* Register map */
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typedef struct regMap {
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uint8_t i2c_reg; /* I2C register */
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uint16_t tis_reg; /* TIS register */
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const char *reg_name; /* Register name */
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} I2CRegMap;
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/*
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* The register values in the common code is different than the latest
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* register numbers as per the spec hence add the conversion map
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*/
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static const I2CRegMap tpm_tis_reg_map[] = {
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/*
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* These registers are sent to TIS layer. The register with UNKNOWN
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* mapping are not sent to TIS layer and handled in I2c layer.
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* NOTE: Adding frequently used registers at the start
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*/
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{ TPM_I2C_REG_DATA_FIFO, TPM_TIS_REG_DATA_FIFO, "FIFO", },
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{ TPM_I2C_REG_STS, TPM_TIS_REG_STS, "STS", },
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{ TPM_I2C_REG_DATA_CSUM_GET, TPM_I2C_REG_UNKNOWN, "CSUM_GET", },
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{ TPM_I2C_REG_LOC_SEL, TPM_I2C_REG_UNKNOWN, "LOC_SEL", },
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{ TPM_I2C_REG_ACCESS, TPM_TIS_REG_ACCESS, "ACCESS", },
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{ TPM_I2C_REG_INT_ENABLE, TPM_TIS_REG_INT_ENABLE, "INTR_ENABLE",},
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{ TPM_I2C_REG_INT_CAPABILITY, TPM_I2C_REG_UNKNOWN, "INTR_CAP", },
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{ TPM_I2C_REG_INTF_CAPABILITY, TPM_TIS_REG_INTF_CAPABILITY, "INTF_CAP", },
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{ TPM_I2C_REG_DID_VID, TPM_TIS_REG_DID_VID, "DID_VID", },
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{ TPM_I2C_REG_RID, TPM_TIS_REG_RID, "RID", },
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{ TPM_I2C_REG_I2C_DEV_ADDRESS, TPM_I2C_REG_UNKNOWN, "DEV_ADDRESS",},
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{ TPM_I2C_REG_DATA_CSUM_ENABLE, TPM_I2C_REG_UNKNOWN, "CSUM_ENABLE",},
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};
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static int tpm_tis_i2c_pre_save(void *opaque)
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{
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TPMStateI2C *i2cst = opaque;
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return tpm_tis_pre_save(&i2cst->state);
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}
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static int tpm_tis_i2c_post_load(void *opaque, int version_id)
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{
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TPMStateI2C *i2cst = opaque;
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if (i2cst->offset >= 1) {
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tpm_tis_i2c_to_tis_reg(i2cst, i2cst->data[0]);
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}
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return 0;
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}
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static const VMStateDescription vmstate_tpm_tis_i2c = {
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.name = "tpm-tis-i2c",
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.version_id = 0,
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.pre_save = tpm_tis_i2c_pre_save,
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.post_load = tpm_tis_i2c_post_load,
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.fields = (const VMStateField[]) {
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VMSTATE_BUFFER(state.buffer, TPMStateI2C),
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VMSTATE_UINT16(state.rw_offset, TPMStateI2C),
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VMSTATE_UINT8(state.active_locty, TPMStateI2C),
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VMSTATE_UINT8(state.aborting_locty, TPMStateI2C),
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VMSTATE_UINT8(state.next_locty, TPMStateI2C),
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VMSTATE_STRUCT_ARRAY(state.loc, TPMStateI2C, TPM_TIS_NUM_LOCALITIES, 0,
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vmstate_locty, TPMLocality),
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/* i2c specifics */
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VMSTATE_UINT8(offset, TPMStateI2C),
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VMSTATE_UINT8(operation, TPMStateI2C),
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VMSTATE_BUFFER(data, TPMStateI2C),
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VMSTATE_UINT8(loc_sel, TPMStateI2C),
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VMSTATE_UINT8(csum_enable, TPMStateI2C),
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VMSTATE_END_OF_LIST()
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}
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};
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/*
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* Set data value. The i2cst->offset is not updated as called in
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* the read path.
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*/
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static void tpm_tis_i2c_set_data(TPMStateI2C *i2cst, uint32_t data)
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{
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i2cst->data[1] = data;
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i2cst->data[2] = data >> 8;
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i2cst->data[3] = data >> 16;
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i2cst->data[4] = data >> 24;
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}
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/*
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* Generate interface capability based on what is returned by TIS and what is
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* expected by I2C. Save the capability in the data array overwriting the TIS
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* capability.
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*/
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static uint32_t tpm_tis_i2c_interface_capability(TPMStateI2C *i2cst,
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uint32_t tis_cap)
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{
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uint32_t i2c_cap;
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/* Now generate i2c capability */
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i2c_cap = (TPM_I2C_CAP_INTERFACE_TYPE |
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TPM_I2C_CAP_INTERFACE_VER |
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TPM_I2C_CAP_TPM2_FAMILY |
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TPM_I2C_CAP_LOCALITY_CAP |
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TPM_I2C_CAP_BUS_SPEED |
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TPM_I2C_CAP_DEV_ADDR_CHANGE);
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/* Now check the TIS and set some capabilities */
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/* Static burst count set */
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if (tis_cap & TPM_TIS_CAP_BURST_COUNT_STATIC) {
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i2c_cap |= TPM_I2C_CAP_BURST_COUNT_STATIC;
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}
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return i2c_cap;
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}
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/* Convert I2C register to TIS address and returns the name of the register */
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static inline void tpm_tis_i2c_to_tis_reg(TPMStateI2C *i2cst, uint8_t i2c_reg)
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{
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const I2CRegMap *reg_map;
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int i;
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i2cst->tis_addr = 0xffffffff;
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/* Special case for the STS register. */
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if (i2c_reg >= TPM_I2C_REG_STS && i2c_reg <= TPM_I2C_REG_STS + 3) {
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i2c_reg = TPM_I2C_REG_STS;
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}
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for (i = 0; i < ARRAY_SIZE(tpm_tis_reg_map); i++) {
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reg_map = &tpm_tis_reg_map[i];
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if (reg_map->i2c_reg == i2c_reg) {
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i2cst->reg_name = reg_map->reg_name;
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i2cst->tis_addr = reg_map->tis_reg;
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/* Include the locality in the address. */
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assert(TPM_TIS_I2C_IS_VALID_LOCTY(i2cst->loc_sel));
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i2cst->tis_addr += (i2cst->loc_sel << TPM_TIS_LOCALITY_SHIFT);
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break;
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}
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}
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}
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/* Clear some fields from the structure. */
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static inline void tpm_tis_i2c_clear_data(TPMStateI2C *i2cst)
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{
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/* Clear operation and offset */
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i2cst->operation = 0;
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i2cst->offset = 0;
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i2cst->tis_addr = 0xffffffff;
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i2cst->reg_name = NULL;
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memset(i2cst->data, 0, sizeof(i2cst->data));
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return;
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}
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/* Send data to TPM */
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static inline void tpm_tis_i2c_tpm_send(TPMStateI2C *i2cst)
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{
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uint32_t data;
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size_t offset = 0;
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uint32_t sz = 4;
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if ((i2cst->operation == OP_SEND) && (i2cst->offset > 1)) {
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switch (i2cst->data[0]) {
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case TPM_I2C_REG_DATA_CSUM_ENABLE:
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/*
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* Checksum is not handled by TIS code hence we will consume the
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* register here.
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*/
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i2cst->csum_enable = i2cst->data[1] & TPM_DATA_CSUM_ENABLED;
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break;
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case TPM_I2C_REG_DATA_FIFO:
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/* Handled in the main i2c_send function */
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break;
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case TPM_I2C_REG_LOC_SEL:
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/*
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* This register is not handled by TIS so save the locality
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* locally
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*/
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if (TPM_TIS_I2C_IS_VALID_LOCTY(i2cst->data[1])) {
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i2cst->loc_sel = i2cst->data[1];
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}
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break;
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default:
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/* We handle non-FIFO here */
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/* Index 0 is a register. Convert byte stream to uint32_t */
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data = i2cst->data[1];
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data |= i2cst->data[2] << 8;
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data |= i2cst->data[3] << 16;
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data |= i2cst->data[4] << 24;
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/* Add register specific masking */
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switch (i2cst->data[0]) {
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case TPM_I2C_REG_INT_ENABLE:
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data &= TPM_I2C_INT_ENABLE_MASK;
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break;
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case TPM_I2C_REG_STS ... TPM_I2C_REG_STS + 3:
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/*
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* STS register has 4 bytes data.
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* As per the specs following writes must be allowed.
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* - From base address 1 to 4 bytes are allowed.
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* - Single byte write to first or last byte must
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* be allowed.
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*/
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offset = i2cst->data[0] - TPM_I2C_REG_STS;
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if (offset > 0) {
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sz = 1;
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}
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data &= (TPM_I2C_STS_WRITE_MASK >> (offset * 8));
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break;
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}
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tpm_tis_write_data(&i2cst->state, i2cst->tis_addr + offset, data,
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sz);
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break;
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}
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tpm_tis_i2c_clear_data(i2cst);
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}
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return;
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}
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/* Callback from TPM to indicate that response is copied */
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static void tpm_tis_i2c_request_completed(TPMIf *ti, int ret)
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{
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TPMStateI2C *i2cst = TPM_TIS_I2C(ti);
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TPMState *s = &i2cst->state;
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/* Inform the common code. */
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tpm_tis_request_completed(s, ret);
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}
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static enum TPMVersion tpm_tis_i2c_get_tpm_version(TPMIf *ti)
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{
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TPMStateI2C *i2cst = TPM_TIS_I2C(ti);
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TPMState *s = &i2cst->state;
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return tpm_tis_get_tpm_version(s);
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}
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static int tpm_tis_i2c_event(I2CSlave *i2c, enum i2c_event event)
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{
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TPMStateI2C *i2cst = TPM_TIS_I2C(i2c);
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int ret = 0;
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switch (event) {
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case I2C_START_RECV:
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trace_tpm_tis_i2c_event("START_RECV");
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break;
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case I2C_START_SEND:
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trace_tpm_tis_i2c_event("START_SEND");
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tpm_tis_i2c_clear_data(i2cst);
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break;
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case I2C_FINISH:
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trace_tpm_tis_i2c_event("FINISH");
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if (i2cst->operation == OP_SEND) {
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tpm_tis_i2c_tpm_send(i2cst);
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} else {
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tpm_tis_i2c_clear_data(i2cst);
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}
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break;
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default:
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break;
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}
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return ret;
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}
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/*
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* If data is for FIFO then it is received from tpm_tis_common buffer
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* otherwise it will be handled using single call to common code and
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* cached in the local buffer.
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*/
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static uint8_t tpm_tis_i2c_recv(I2CSlave *i2c)
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{
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int ret = 0;
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uint32_t data_read;
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TPMStateI2C *i2cst = TPM_TIS_I2C(i2c);
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TPMState *s = &i2cst->state;
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uint16_t i2c_reg = i2cst->data[0];
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size_t offset;
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if (i2cst->operation == OP_RECV) {
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/* Do not cache FIFO data. */
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if (i2cst->data[0] == TPM_I2C_REG_DATA_FIFO) {
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data_read = tpm_tis_read_data(s, i2cst->tis_addr, 1);
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ret = (data_read & 0xff);
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} else if (i2cst->offset < sizeof(i2cst->data)) {
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ret = i2cst->data[i2cst->offset++];
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}
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} else if ((i2cst->operation == OP_SEND) && (i2cst->offset < 2)) {
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/* First receive call after send */
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i2cst->operation = OP_RECV;
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switch (i2c_reg) {
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case TPM_I2C_REG_LOC_SEL:
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/* Location selection register is managed by i2c */
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tpm_tis_i2c_set_data(i2cst, i2cst->loc_sel);
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break;
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case TPM_I2C_REG_DATA_FIFO:
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/* FIFO data is directly read from TPM TIS */
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data_read = tpm_tis_read_data(s, i2cst->tis_addr, 1);
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tpm_tis_i2c_set_data(i2cst, (data_read & 0xff));
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break;
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case TPM_I2C_REG_DATA_CSUM_ENABLE:
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tpm_tis_i2c_set_data(i2cst, i2cst->csum_enable);
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break;
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case TPM_I2C_REG_INT_CAPABILITY:
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/*
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* Interrupt is not supported in the linux kernel hence we cannot
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* test this model with interrupts.
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*/
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tpm_tis_i2c_set_data(i2cst, TPM_I2C_INT_ENABLE_MASK);
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break;
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case TPM_I2C_REG_DATA_CSUM_GET:
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/*
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* Checksum registers are not supported by common code hence
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* call a common code to get the checksum.
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*/
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data_read = tpm_tis_get_checksum(s);
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/* Save the byte stream in data field */
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tpm_tis_i2c_set_data(i2cst, data_read);
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break;
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default:
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data_read = tpm_tis_read_data(s, i2cst->tis_addr, 4);
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switch (i2c_reg) {
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case TPM_I2C_REG_INTF_CAPABILITY:
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/* Prepare the capabilities as per I2C interface */
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data_read = tpm_tis_i2c_interface_capability(i2cst,
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data_read);
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break;
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case TPM_I2C_REG_STS ... TPM_I2C_REG_STS + 3:
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offset = i2c_reg - TPM_I2C_REG_STS;
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/*
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* As per specs, STS bit 31:26 are reserved and must
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* be set to 0
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*/
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data_read &= TPM_I2C_STS_READ_MASK;
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/*
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* STS register has 4 bytes data.
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* As per the specs following reads must be allowed.
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* - From base address 1 to 4 bytes are allowed.
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* - Last byte must be allowed to read as a single byte
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* - Second and third byte must be allowed to read as two
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* two bytes.
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*/
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data_read >>= (offset * 8);
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break;
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}
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/* Save byte stream in data[] */
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tpm_tis_i2c_set_data(i2cst, data_read);
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break;
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}
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/* Return first byte with this call */
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i2cst->offset = 1; /* keep the register value intact for debug */
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ret = i2cst->data[i2cst->offset++];
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} else {
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i2cst->operation = OP_RECV;
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}
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trace_tpm_tis_i2c_recv(ret);
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return ret;
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}
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/*
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* Send function only remembers data in the buffer and then calls
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* TPM TIS common code during FINISH event.
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*/
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static int tpm_tis_i2c_send(I2CSlave *i2c, uint8_t data)
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{
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TPMStateI2C *i2cst = TPM_TIS_I2C(i2c);
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/* Reject non-supported registers. */
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if (i2cst->offset == 0) {
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/* Convert I2C register to TIS register */
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tpm_tis_i2c_to_tis_reg(i2cst, data);
|
|
if (i2cst->tis_addr == 0xffffffff) {
|
|
return 0xffffffff;
|
|
}
|
|
|
|
trace_tpm_tis_i2c_send_reg(i2cst->reg_name, data);
|
|
|
|
/* We do not support device address change */
|
|
if (data == TPM_I2C_REG_I2C_DEV_ADDRESS) {
|
|
qemu_log_mask(LOG_UNIMP, "%s: Device address change "
|
|
"is not supported.\n", __func__);
|
|
return 0xffffffff;
|
|
}
|
|
} else {
|
|
trace_tpm_tis_i2c_send(data);
|
|
}
|
|
|
|
if (i2cst->offset < sizeof(i2cst->data)) {
|
|
i2cst->operation = OP_SEND;
|
|
|
|
/*
|
|
* In two cases, we save values in the local buffer.
|
|
* 1) The first value is always a register.
|
|
* 2) In case of non-FIFO multibyte registers, TIS expects full
|
|
* register value hence I2C layer cache the register value and send
|
|
* to TIS during FINISH event.
|
|
*/
|
|
if ((i2cst->offset == 0) ||
|
|
(i2cst->data[0] != TPM_I2C_REG_DATA_FIFO)) {
|
|
i2cst->data[i2cst->offset++] = data;
|
|
} else {
|
|
/*
|
|
* The TIS can process FIFO data one byte at a time hence the FIFO
|
|
* data is sent to TIS directly.
|
|
*/
|
|
tpm_tis_write_data(&i2cst->state, i2cst->tis_addr, data, 1);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Return non-zero to indicate NAK */
|
|
return 1;
|
|
}
|
|
|
|
static Property tpm_tis_i2c_properties[] = {
|
|
DEFINE_PROP_TPMBE("tpmdev", TPMStateI2C, state.be_driver),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void tpm_tis_i2c_realizefn(DeviceState *dev, Error **errp)
|
|
{
|
|
TPMStateI2C *i2cst = TPM_TIS_I2C(dev);
|
|
TPMState *s = &i2cst->state;
|
|
|
|
if (!tpm_find()) {
|
|
error_setg(errp, "at most one TPM device is permitted");
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Get the backend pointer. It is not initialized properly during
|
|
* device_class_set_props
|
|
*/
|
|
s->be_driver = qemu_find_tpm_be("tpm0");
|
|
|
|
if (!s->be_driver) {
|
|
error_setg(errp, "'tpmdev' property is required");
|
|
return;
|
|
}
|
|
}
|
|
|
|
static void tpm_tis_i2c_reset(DeviceState *dev)
|
|
{
|
|
TPMStateI2C *i2cst = TPM_TIS_I2C(dev);
|
|
TPMState *s = &i2cst->state;
|
|
|
|
tpm_tis_i2c_clear_data(i2cst);
|
|
|
|
i2cst->csum_enable = 0;
|
|
i2cst->loc_sel = 0x00;
|
|
|
|
return tpm_tis_reset(s);
|
|
}
|
|
|
|
static void tpm_tis_i2c_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
|
|
TPMIfClass *tc = TPM_IF_CLASS(klass);
|
|
|
|
dc->realize = tpm_tis_i2c_realizefn;
|
|
device_class_set_legacy_reset(dc, tpm_tis_i2c_reset);
|
|
dc->vmsd = &vmstate_tpm_tis_i2c;
|
|
device_class_set_props(dc, tpm_tis_i2c_properties);
|
|
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
|
|
|
|
k->event = tpm_tis_i2c_event;
|
|
k->recv = tpm_tis_i2c_recv;
|
|
k->send = tpm_tis_i2c_send;
|
|
|
|
tc->model = TPM_MODEL_TPM_TIS;
|
|
tc->request_completed = tpm_tis_i2c_request_completed;
|
|
tc->get_version = tpm_tis_i2c_get_tpm_version;
|
|
}
|
|
|
|
static const TypeInfo tpm_tis_i2c_info = {
|
|
.name = TYPE_TPM_TIS_I2C,
|
|
.parent = TYPE_I2C_SLAVE,
|
|
.instance_size = sizeof(TPMStateI2C),
|
|
.class_init = tpm_tis_i2c_class_init,
|
|
.interfaces = (InterfaceInfo[]) {
|
|
{ TYPE_TPM_IF },
|
|
{ }
|
|
}
|
|
};
|
|
|
|
static void tpm_tis_i2c_register_types(void)
|
|
{
|
|
type_register_static(&tpm_tis_i2c_info);
|
|
}
|
|
|
|
type_init(tpm_tis_i2c_register_types)
|