2bf79222ce
Added definitions for RISC-V register structures, including general-purpose registers and floating-point registers, in 'target_arch_reg.h'. Implemented the 'target_copy_regs' function to copy register values from the CPU state to the target register structure, ensuring proper endianness handling using 'tswapreg'. Signed-off-by: Mark Corbin <mark@dibsco.co.uk> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240916155119.14610-7-itachis@FreeBSD.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
89 lines
3.0 KiB
C
89 lines
3.0 KiB
C
/*
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* RISC-V register structures
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*
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* Copyright (c) 2019 Mark Corbin
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef TARGET_ARCH_REG_H
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#define TARGET_ARCH_REG_H
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/* Compare with riscv/include/reg.h */
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typedef struct target_reg {
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uint64_t ra; /* return address */
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uint64_t sp; /* stack pointer */
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uint64_t gp; /* global pointer */
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uint64_t tp; /* thread pointer */
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uint64_t t[7]; /* temporaries */
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uint64_t s[12]; /* saved registers */
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uint64_t a[8]; /* function arguments */
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uint64_t sepc; /* exception program counter */
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uint64_t sstatus; /* status register */
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} target_reg_t;
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typedef struct target_fpreg {
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uint64_t fp_x[32][2]; /* Floating point registers */
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uint64_t fp_fcsr; /* Floating point control reg */
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} target_fpreg_t;
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#define tswapreg(ptr) tswapal(ptr)
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/* Compare with struct trapframe in riscv/include/frame.h */
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static inline void target_copy_regs(target_reg_t *regs,
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const CPURISCVState *env)
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{
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regs->ra = tswapreg(env->gpr[1]);
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regs->sp = tswapreg(env->gpr[2]);
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regs->gp = tswapreg(env->gpr[3]);
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regs->tp = tswapreg(env->gpr[4]);
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regs->t[0] = tswapreg(env->gpr[5]);
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regs->t[1] = tswapreg(env->gpr[6]);
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regs->t[2] = tswapreg(env->gpr[7]);
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regs->t[3] = tswapreg(env->gpr[28]);
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regs->t[4] = tswapreg(env->gpr[29]);
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regs->t[5] = tswapreg(env->gpr[30]);
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regs->t[6] = tswapreg(env->gpr[31]);
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regs->s[0] = tswapreg(env->gpr[8]);
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regs->s[1] = tswapreg(env->gpr[9]);
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regs->s[2] = tswapreg(env->gpr[18]);
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regs->s[3] = tswapreg(env->gpr[19]);
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regs->s[4] = tswapreg(env->gpr[20]);
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regs->s[5] = tswapreg(env->gpr[21]);
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regs->s[6] = tswapreg(env->gpr[22]);
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regs->s[7] = tswapreg(env->gpr[23]);
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regs->s[8] = tswapreg(env->gpr[24]);
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regs->s[9] = tswapreg(env->gpr[25]);
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regs->s[10] = tswapreg(env->gpr[26]);
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regs->s[11] = tswapreg(env->gpr[27]);
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regs->a[0] = tswapreg(env->gpr[10]);
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regs->a[1] = tswapreg(env->gpr[11]);
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regs->a[2] = tswapreg(env->gpr[12]);
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regs->a[3] = tswapreg(env->gpr[13]);
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regs->a[4] = tswapreg(env->gpr[14]);
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regs->a[5] = tswapreg(env->gpr[15]);
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regs->a[6] = tswapreg(env->gpr[16]);
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regs->a[7] = tswapreg(env->gpr[17]);
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regs->sepc = tswapreg(env->pc);
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}
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#undef tswapreg
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#endif /* TARGET_ARCH_REG_H */
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