94fc95cdb2
Only relevant on PowerPC targets, for now. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2468 c046a42c-6fe2-441c-8c8c-71466251a162
331 lines
11 KiB
C
331 lines
11 KiB
C
/*
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* QEMU Sun4m System Emulator
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h"
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#define KERNEL_LOAD_ADDR 0x00004000
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#define CMDLINE_ADDR 0x007ff000
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#define INITRD_LOAD_ADDR 0x00800000
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#define PROM_SIZE_MAX (256 * 1024)
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#define PROM_ADDR 0xffd00000
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#define PROM_FILENAME "openbios-sparc32"
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#define PHYS_JJ_EEPROM 0x71200000 /* m48t08 */
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#define PHYS_JJ_IDPROM_OFF 0x1FD8
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#define PHYS_JJ_EEPROM_SIZE 0x2000
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// IRQs are not PIL ones, but master interrupt controller register
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// bits
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#define PHYS_JJ_IOMMU 0x10000000 /* I/O MMU */
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#define PHYS_JJ_TCX_FB 0x50000000 /* TCX frame buffer */
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#define PHYS_JJ_SLAVIO 0x70000000 /* Slavio base */
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#define PHYS_JJ_DMA 0x78400000 /* DMA controller */
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#define PHYS_JJ_ESP 0x78800000 /* ESP SCSI */
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#define PHYS_JJ_ESP_IRQ 18
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#define PHYS_JJ_LE 0x78C00000 /* Lance ethernet */
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#define PHYS_JJ_LE_IRQ 16
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#define PHYS_JJ_CLOCK 0x71D00000 /* Per-CPU timer/counter, L14 */
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#define PHYS_JJ_CLOCK_IRQ 7
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#define PHYS_JJ_CLOCK1 0x71D10000 /* System timer/counter, L10 */
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#define PHYS_JJ_CLOCK1_IRQ 19
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#define PHYS_JJ_INTR0 0x71E00000 /* Per-CPU interrupt control registers */
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#define PHYS_JJ_INTR_G 0x71E10000 /* Master interrupt control registers */
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#define PHYS_JJ_MS_KBD 0x71000000 /* Mouse and keyboard */
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#define PHYS_JJ_MS_KBD_IRQ 14
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#define PHYS_JJ_SER 0x71100000 /* Serial */
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#define PHYS_JJ_SER_IRQ 15
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#define PHYS_JJ_FDC 0x71400000 /* Floppy */
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#define PHYS_JJ_FLOPPY_IRQ 22
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#define PHYS_JJ_ME_IRQ 30 /* Module error, power fail */
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#define PHYS_JJ_CS 0x6c000000 /* Crystal CS4231 */
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#define PHYS_JJ_CS_IRQ 5
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#define MAX_CPUS 16
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/* TSC handling */
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uint64_t cpu_get_tsc()
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{
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return qemu_get_clock(vm_clock);
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}
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int DMA_get_channel_mode (int nchan)
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{
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return 0;
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}
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int DMA_read_memory (int nchan, void *buf, int pos, int size)
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{
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return 0;
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}
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int DMA_write_memory (int nchan, void *buf, int pos, int size)
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{
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return 0;
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}
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void DMA_hold_DREQ (int nchan) {}
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void DMA_release_DREQ (int nchan) {}
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void DMA_schedule(int nchan) {}
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void DMA_run (void) {}
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void DMA_init (int high_page_enable) {}
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void DMA_register_channel (int nchan,
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DMA_transfer_handler transfer_handler,
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void *opaque)
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{
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}
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static void nvram_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
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{
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m48t59_write(nvram, addr++, (value >> 8) & 0xff);
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m48t59_write(nvram, addr++, value & 0xff);
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}
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static void nvram_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
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{
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m48t59_write(nvram, addr++, value >> 24);
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m48t59_write(nvram, addr++, (value >> 16) & 0xff);
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m48t59_write(nvram, addr++, (value >> 8) & 0xff);
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m48t59_write(nvram, addr++, value & 0xff);
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}
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static void nvram_set_string (m48t59_t *nvram, uint32_t addr,
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const unsigned char *str, uint32_t max)
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{
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unsigned int i;
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for (i = 0; i < max && str[i] != '\0'; i++) {
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m48t59_write(nvram, addr + i, str[i]);
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}
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m48t59_write(nvram, addr + max - 1, '\0');
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}
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static m48t59_t *nvram;
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extern int nographic;
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static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
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int boot_device, uint32_t RAM_size,
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uint32_t kernel_size,
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int width, int height, int depth)
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{
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unsigned char tmp = 0;
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int i, j;
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// Try to match PPC NVRAM
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nvram_set_string(nvram, 0x00, "QEMU_BIOS", 16);
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nvram_set_lword(nvram, 0x10, 0x00000001); /* structure v1 */
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// NVRAM_size, arch not applicable
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m48t59_write(nvram, 0x2D, smp_cpus & 0xff);
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m48t59_write(nvram, 0x2E, 0);
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m48t59_write(nvram, 0x2F, nographic & 0xff);
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nvram_set_lword(nvram, 0x30, RAM_size);
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m48t59_write(nvram, 0x34, boot_device & 0xff);
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nvram_set_lword(nvram, 0x38, KERNEL_LOAD_ADDR);
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nvram_set_lword(nvram, 0x3C, kernel_size);
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if (cmdline) {
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strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
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nvram_set_lword(nvram, 0x40, CMDLINE_ADDR);
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nvram_set_lword(nvram, 0x44, strlen(cmdline));
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}
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// initrd_image, initrd_size passed differently
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nvram_set_word(nvram, 0x54, width);
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nvram_set_word(nvram, 0x56, height);
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nvram_set_word(nvram, 0x58, depth);
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// Sun4m specific use
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i = 0x1fd8;
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m48t59_write(nvram, i++, 0x01);
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m48t59_write(nvram, i++, 0x80); /* Sun4m OBP */
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j = 0;
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m48t59_write(nvram, i++, macaddr[j++]);
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m48t59_write(nvram, i++, macaddr[j++]);
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m48t59_write(nvram, i++, macaddr[j++]);
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m48t59_write(nvram, i++, macaddr[j++]);
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m48t59_write(nvram, i++, macaddr[j++]);
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m48t59_write(nvram, i, macaddr[j]);
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/* Calculate checksum */
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for (i = 0x1fd8; i < 0x1fe7; i++) {
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tmp ^= m48t59_read(nvram, i);
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}
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m48t59_write(nvram, 0x1fe7, tmp);
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}
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static void *slavio_intctl;
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void pic_info()
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{
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slavio_pic_info(slavio_intctl);
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}
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void irq_info()
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{
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slavio_irq_info(slavio_intctl);
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}
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void pic_set_irq(int irq, int level)
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{
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slavio_pic_set_irq(slavio_intctl, irq, level);
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}
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void pic_set_irq_new(void *opaque, int irq, int level)
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{
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pic_set_irq(irq, level);
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}
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void pic_set_irq_cpu(int irq, int level, unsigned int cpu)
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{
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slavio_pic_set_irq_cpu(slavio_intctl, irq, level, cpu);
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}
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static void *slavio_misc;
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void qemu_system_powerdown(void)
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{
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slavio_set_power_fail(slavio_misc, 1);
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}
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static void main_cpu_reset(void *opaque)
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{
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CPUState *env = opaque;
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cpu_reset(env);
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}
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/* Sun4m hardware initialisation */
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static void sun4m_init(int ram_size, int vga_ram_size, int boot_device,
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DisplayState *ds, const char **fd_filename, int snapshot,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model)
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{
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CPUState *env, *envs[MAX_CPUS];
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char buf[1024];
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int ret, linux_boot;
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unsigned int i;
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long vram_size = 0x100000, prom_offset, initrd_size, kernel_size;
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void *iommu, *dma, *main_esp, *main_lance = NULL;
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linux_boot = (kernel_filename != NULL);
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/* init CPUs */
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for(i = 0; i < smp_cpus; i++) {
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env = cpu_init();
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envs[i] = env;
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if (i != 0)
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env->halted = 1;
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register_savevm("cpu", i, 3, cpu_save, cpu_load, env);
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qemu_register_reset(main_cpu_reset, env);
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}
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/* allocate RAM */
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cpu_register_physical_memory(0, ram_size, 0);
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iommu = iommu_init(PHYS_JJ_IOMMU);
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slavio_intctl = slavio_intctl_init(PHYS_JJ_INTR0, PHYS_JJ_INTR_G);
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for(i = 0; i < smp_cpus; i++) {
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slavio_intctl_set_cpu(slavio_intctl, i, envs[i]);
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}
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dma = sparc32_dma_init(PHYS_JJ_DMA, PHYS_JJ_ESP_IRQ, PHYS_JJ_LE_IRQ, iommu, slavio_intctl);
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tcx_init(ds, PHYS_JJ_TCX_FB, phys_ram_base + ram_size, ram_size, vram_size, graphic_width, graphic_height);
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if (nd_table[0].vlan) {
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if (nd_table[0].model == NULL
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|| strcmp(nd_table[0].model, "lance") == 0) {
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main_lance = lance_init(&nd_table[0], PHYS_JJ_LE, dma);
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} else {
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fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
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exit (1);
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}
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}
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nvram = m48t59_init(0, PHYS_JJ_EEPROM, 0, PHYS_JJ_EEPROM_SIZE, 8);
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for (i = 0; i < MAX_CPUS; i++) {
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slavio_timer_init(PHYS_JJ_CLOCK + i * TARGET_PAGE_SIZE, PHYS_JJ_CLOCK_IRQ, 0, i);
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}
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slavio_timer_init(PHYS_JJ_CLOCK1, PHYS_JJ_CLOCK1_IRQ, 2, (unsigned int)-1);
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slavio_serial_ms_kbd_init(PHYS_JJ_MS_KBD, PHYS_JJ_MS_KBD_IRQ);
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// Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
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// Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
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slavio_serial_init(PHYS_JJ_SER, PHYS_JJ_SER_IRQ, serial_hds[1], serial_hds[0]);
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fdctrl_init(PHYS_JJ_FLOPPY_IRQ, 0, 1, PHYS_JJ_FDC, fd_table);
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main_esp = esp_init(bs_table, PHYS_JJ_ESP, dma);
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for (i = 0; i < MAX_DISKS; i++) {
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if (bs_table[i]) {
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esp_scsi_attach(main_esp, bs_table[i], i);
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}
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}
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slavio_misc = slavio_misc_init(PHYS_JJ_SLAVIO, PHYS_JJ_ME_IRQ);
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cs_init(PHYS_JJ_CS, PHYS_JJ_CS_IRQ, slavio_intctl);
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sparc32_dma_set_reset_data(dma, main_esp, main_lance);
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prom_offset = ram_size + vram_size;
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cpu_register_physical_memory(PROM_ADDR,
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(PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK,
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prom_offset | IO_MEM_ROM);
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snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAME);
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ret = load_elf(buf, 0, NULL);
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if (ret < 0) {
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fprintf(stderr, "qemu: could not load prom '%s'\n",
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buf);
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exit(1);
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}
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kernel_size = 0;
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if (linux_boot) {
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kernel_size = load_elf(kernel_filename, -0xf0000000, NULL);
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if (kernel_size < 0)
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kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
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if (kernel_size < 0)
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kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
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if (kernel_size < 0) {
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fprintf(stderr, "qemu: could not load kernel '%s'\n",
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kernel_filename);
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exit(1);
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}
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/* load initrd */
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initrd_size = 0;
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if (initrd_filename) {
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initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
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if (initrd_size < 0) {
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fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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initrd_filename);
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exit(1);
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}
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}
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if (initrd_size > 0) {
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for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
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if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
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== 0x48647253) { // HdrS
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stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
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stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
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break;
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}
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}
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}
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}
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nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline, boot_device, ram_size, kernel_size, graphic_width, graphic_height, graphic_depth);
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}
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QEMUMachine sun4m_machine = {
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"sun4m",
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"Sun4m platform",
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sun4m_init,
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};
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