Alistair Francis 94c6ba83c1 target/riscv: Fix the PMP is locked check when using TOR ...

The RISC-V spec says:
    if PMP entry i is locked and pmpicfg.A is set to TOR, writes to
    pmpaddri-1 are ignored.

The current QEMU code ignores accesses to pmpaddri-1 and pmpcfgi-1 which
is incorrect.

Update the pmp_is_locked() function to not check the supporting fields
and instead enforce the lock functionality in the pmpaddr write operation.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 2831241458163f445a89bd59c59990247265b0c6.1618812899.git.alistair.francis@wdc.com

2021-05-11 20:02:06 +10:00

..

insn_trans

riscv: Add semihosting support

2021-01-18 10:05:06 +00:00

arch_dump.c

target-riscv: support QMP dump-guest-memory

2021-03-04 09:43:29 -05:00

cpu_bits.h

target/riscv: Convert the RISC-V exceptions to an enum

2021-05-11 20:02:06 +10:00

cpu_helper.c

riscv: don't look at SUM when accessing memory from a debugger context

2021-05-11 20:02:06 +10:00

cpu_user.h

…

cpu-param.h

target/riscv: Add a virtualised MMU Mode

2020-11-09 15:08:45 -08:00

cpu.c

target/riscv: Convert the RISC-V exceptions to an enum

2021-05-11 20:02:06 +10:00

cpu.h

target/riscv: Use RISCVException enum for CSR access

2021-05-11 20:02:06 +10:00

csr.c

target/riscv: Use RISCVException enum for CSR access

2021-05-11 20:02:06 +10:00

fpu_helper.c

target/riscv: fpu_helper: Match function defs in HELPER macros

2020-12-17 21:56:44 -08:00

gdbstub.c

target/riscv: Use RISCVException enum for CSR access

2021-05-11 20:02:06 +10:00

helper.h

target/riscv: fpu_helper: Match function defs in HELPER macros

2020-12-17 21:56:44 -08:00

insn16-32.decode

…

insn16-64.decode

…

insn16.decode

…

insn32-64.decode

target/riscv: Allow generating hlv/hlvx/hsv instructions

2020-08-25 09:11:35 -07:00

insn32.decode

target/riscv: Allow generating hlv/hlvx/hsv instructions

2020-08-25 09:11:35 -07:00

instmap.h

…

internals.h

target/riscv: Add basic vmstate description of CPU

2020-11-03 07:17:23 -08:00

machine.c

target/riscv: Remove privilege v1.9 specific CSR related code

2021-05-11 20:01:10 +10:00

meson.build

target-riscv: support QMP dump-guest-memory

2021-03-04 09:43:29 -05:00

monitor.c

hmp: Pass monitor to mon_get_cpu_env()

2020-11-13 12:45:51 +00:00

op_helper.c

target/riscv: Use RISCVException enum for CSR access

2021-05-11 20:02:06 +10:00

pmp.c

target/riscv: Fix the PMP is locked check when using TOR

2021-05-11 20:02:06 +10:00

pmp.h

target/riscv: propagate PMP permission to TLB page

2021-03-22 21:54:40 -04:00

trace-events

trace-events: Fix attribution of trace points to source

2020-09-09 17:17:58 +01:00

trace.h

…

translate.c

target/riscv: Remove privilege v1.9 specific CSR related code

2021-05-11 20:01:10 +10:00

vector_helper.c

target/riscv: Fixup saturate subtract function

2021-05-11 20:02:06 +10:00