Weiwei Li 94bdf6ee10 target/riscv: Simplify the check for Zfhmin and Zhinxmin ... We needn't check Zfh and Zhinx in these instructions. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20230215020539.4788-4-liweiwei@iscas.ac.cn> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>		2023-03-01 14:57:32 -08:00
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trans_privileged.c.inc	target/riscv: Add itrigger support when icount is not enabled	2023-01-06 10:42:55 +10:00
trans_rva.c.inc	target/riscv: Ensure opcode is saved for all relevant instructions	2023-02-07 08:19:23 +10:00
trans_rvb.c.inc	target/riscv: fix ctzw behavior	2023-02-07 08:19:23 +10:00
trans_rvd.c.inc	target/riscv: Ensure opcode is saved for all relevant instructions	2023-02-07 08:19:23 +10:00
trans_rvf.c.inc	target/riscv: Ensure opcode is saved for all relevant instructions	2023-02-07 08:19:23 +10:00
trans_rvh.c.inc	target/riscv: Ensure opcode is saved for all relevant instructions	2023-02-07 08:19:23 +10:00
trans_rvi.c.inc	target/riscv: Ensure opcode is saved for all relevant instructions	2023-02-07 08:19:23 +10:00
trans_rvk.c.inc	target/riscv: rvk: add support for zksed/zksh extension	2022-04-29 10:47:45 +10:00
trans_rvm.c.inc	target/riscv: add support for zmmul extension v0.1	2022-06-10 09:31:42 +10:00
trans_rvv.c.inc	target/riscv: Introduce helper_set_rounding_mode_chkfrm	2023-01-20 10:14:14 +10:00
trans_rvzawrs.c.inc	RISC-V: Add Zawrs ISA extension support	2023-01-06 10:42:55 +10:00
trans_rvzfh.c.inc	target/riscv: Simplify the check for Zfhmin and Zhinxmin	2023-03-01 14:57:32 -08:00
trans_svinval.c.inc	target/riscv: Ensure opcode is saved for all relevant instructions	2023-02-07 08:19:23 +10:00
trans_xthead.c.inc	RISC-V: Adding XTheadFmv ISA extension	2023-02-07 08:19:23 +10:00
trans_xventanacondops.c.inc	target/riscv: Add XVentanaCondOps custom extension	2022-02-16 12:24:18 +10:00